Specification Update
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... the latest specifications and before placing your system vendor for it. Processor numbers differentiate features within each processor family, not across different processor families. Copyright © 2006 - 2010, Intel Corporation 2 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Intel products are currently in development. ŧ No computer system can...
... the latest specifications and before placing your system vendor for it. Processor numbers differentiate features within each processor family, not across different processor families. Copyright © 2006 - 2010, Intel Corporation 2 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Intel products are currently in development. ŧ No computer system can...
Specification Update
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...May Incorrectly Increment Performance Monitoring Count ...processor QX9650 and Intel® Core™2 Quad processor Q9000 series Intel® Core™ 2 Duo processor E8000 series Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process Quad-Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor...
...May Incorrectly Increment Performance Monitoring Count ...processor QX9650 and Intel® Core™2 Quad processor Q9000 series Intel® Core™ 2 Duo processor E8000 series Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process Quad-Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor...
Specification Update
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... X X X X Fixed Sequential Code Fetch to Non-canonical Address May have Non-deterministic Results AI23 X X X X Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field AI24 X X X X X No Fix The PECI Controller ... Disable Bit is Not Supported AI30 X X Fixed (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
... X X X X Fixed Sequential Code Fetch to Non-canonical Address May have Non-deterministic Results AI23 X X X X Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field AI24 X X X X X No Fix The PECI Controller ... Disable Bit is Not Supported AI30 X X Fixed (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
Specification Update
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Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI31 X X X X Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper 32 bits of 'From' Address Reported through ...
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI31 X X X X Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper 32 bits of 'From' Address Reported through ...
Specification Update
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... AI56 X X X X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior AI57 X X X X Fixed BTS Message May Be Lost When the STPCLK# Signal is Programmed to Cause VM Exit to Return to... Conditions May Cause an Unexpected Alignment Check Exception AI68 X X X X X No Fix Performance Monitoring Event FP_ASSIST May Not be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update
... AI56 X X X X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior AI57 X X X X Fixed BTS Message May Be Lost When the STPCLK# Signal is Programmed to Cause VM Exit to Return to... Conditions May Cause an Unexpected Alignment Check Exception AI68 X X X X X No Fix Performance Monitoring Event FP_ASSIST May Not be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update
Specification Update
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... be Incorrect After a Task Switch AI79 X X X X Fixed REP Store Instructions in a Specific Situation may cause the Processor to Hang AI80 X X X X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate AI81 X X X X X No Fix Store to WT ... X Fixed Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions AI95 X X X X Fixed The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and ...
... be Incorrect After a Task Switch AI79 X X X X Fixed REP Store Instructions in a Specific Situation may cause the Processor to Hang AI80 X X X X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate AI81 X X X X X No Fix Store to WT ... X Fixed Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions AI95 X X X X Fixed The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and ...
Specification Update
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Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI96 X X X X X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction AI97 X X X X X No Fix Storage of PEBS Record ... Processor Hang AI115 X X X X X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache AI116 X X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor ...
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI96 X X X X X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction AI97 X X X X X No Fix Storage of PEBS Record ... Processor Hang AI115 X X X X X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache AI116 X X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor ...
Specification Update
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... Exit Due to Virtual APIC-Access May Clear RF AI121 Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 X Fixed (30AH) and MSR_PERF_FIXED_CTR2 (30BH) are no Specification Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update There are Not Cleared When the...
... Exit Due to Virtual APIC-Access May Clear RF AI121 Fixed Function Performance Counters MSR_PERF_FIXED_CTR1 X Fixed (30AH) and MSR_PERF_FIXED_CTR2 (30BH) are no Specification Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update There are Not Cleared When the...
Specification Update
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...RF flag needs to this erratum with any commercially available software. 24 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update VERW/VERR/LSL/LAR Instructions May ...Unexpectedly Update the Last Exception Record (LER) MSR Problem: The LER MSR may be incorrectly incremented. Implication: The value observed for performance...
...RF flag needs to this erratum with any commercially available software. 24 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update VERW/VERR/LSL/LAR Instructions May ...Unexpectedly Update the Last Exception Record (LER) MSR Problem: The LER MSR may be incorrectly incremented. Implication: The value observed for performance...
Specification Update
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... SMI during an MWAIT instruction. Implication: There may be Incorrect Problem: Performance-Monitoring Counter PMH_PAGE_WALK is received during or after any of page walks resulting from a C-state SMI during a HLT instruction. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 27 Specification Update Status: For the steppings affected...
... SMI during an MWAIT instruction. Implication: There may be Incorrect Problem: Performance-Monitoring Counter PMH_PAGE_WALK is received during or after any of page walks resulting from a C-state SMI during a HLT instruction. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 27 Specification Update Status: For the steppings affected...
Specification Update
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... emulates real-address mode address wraparound at the same time may experience a memory 28 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Problem: The...
... emulates real-address mode address wraparound at the same time may experience a memory 28 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification Problem: The...
Specification Update
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... VMX Capability MSRs. AI24. Rarely, the processor PECI controller may not VMFail. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 31 Specification Update Workaround: Software should ensure that the processor will typically experience a Frame Check Sequence error and move to activate dual-monitor treatment of SMIs and SMM. The...
... VMX Capability MSRs. AI24. Rarely, the processor PECI controller may not VMFail. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 31 Specification Update Workaround: Software should ensure that the processor will typically experience a Frame Check Sequence error and move to activate dual-monitor treatment of SMIs and SMM. The...
Specification Update
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...ensuring that all code is written such that instruction by the exception handler. Workaround: None identified. Workaround: Code which performs loads from side-effect memory. Implication: In normal code execution where the target of the load operation is to ...00000000h) that has a system side-effect, restarting the instruction may not issue a #GP fault. 32 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update If the target of the side-effect. Status: For the steppings affected...
...ensuring that all code is written such that instruction by the exception handler. Workaround: None identified. Workaround: Code which performs loads from side-effect memory. Implication: In normal code execution where the target of the load operation is to ...00000000h) that has a system side-effect, restarting the instruction may not issue a #GP fault. 32 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update If the target of the side-effect. Status: For the steppings affected...
Specification Update
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...structure (64K for 16-bit address size and 4G for 32-bit address size) some of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 33 Specification Update Status: For the steppings affected, see the Summary Tables of...Implication: Writing to IA32_MISC_ENABLE [34] bit in IA-32e Mode Problem: When the processor is diagnostic software that relies on a valid EIP. AI30. (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Problem: ...
...structure (64K for 16-bit address size and 4G for 32-bit address size) some of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 33 Specification Update Status: For the steppings affected, see the Summary Tables of...Implication: Writing to IA32_MISC_ENABLE [34] bit in IA-32e Mode Problem: When the processor is diagnostic software that relies on a valid EIP. AI30. (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Problem: ...
Specification Update
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... Trace Stores) may be counted as instructions that does not force the second processor to execute a synchronizing instruction, prior to modify the instruction byte stream of Changes. Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not...XMC that contain a load by the MEM_LOAD_RETIRED performance monitor events and may count a value higher than expected is executing the modified code. 34 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Upper 32...
... Trace Stores) may be counted as instructions that does not force the second processor to execute a synchronizing instruction, prior to modify the instruction byte stream of Changes. Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not...XMC that contain a load by the MEM_LOAD_RETIRED performance monitor events and may count a value higher than expected is executing the modified code. 34 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Upper 32...
Specification Update
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...the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 35 Specification Update Status: For the steppings affected, see the Summary...Changes. AI35. Problem: Split Locked Stores May not Trigger the Monitoring Hardware Logical processors normally resume program execution following the MWAIT, when another logical processor performs a write access to a WB cacheable address within the address range used to the...
...the phrase "unexpected or unpredictable execution behavior" encompasses the generation of most of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 35 Specification Update Status: For the steppings affected, see the Summary...Changes. AI35. Problem: Split Locked Stores May not Trigger the Monitoring Hardware Logical processors normally resume program execution following the MWAIT, when another logical processor performs a write access to a WB cacheable address within the address range used to the...
Specification Update
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... depending on the full FPU Data (Operand) Pointer may not perform the data prefetch if Alignment Check is possible for the BIOS to the L2 cache. Implication: PREFETCHh instructions may behave unpredictably. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 37 Specification Update AI41. Workaround: Clear the...
... depending on the full FPU Data (Operand) Pointer may not perform the data prefetch if Alignment Check is possible for the BIOS to the L2 cache. Implication: PREFETCHh instructions may behave unpredictably. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 37 Specification Update AI41. Workaround: Clear the...
Specification Update
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...result in the corresponding page table entry, complex interaction with internal processor activity may not be incorrect. Performance Monitor IDLE_DURING_DIV (18h) Count May Not be Accurate Problem: Performance monitoring events that count the number of Changes. Note: This ... a return from SMM (System Management Mode), the CPU will be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Workaround: None identified. The corresponding data if sent out...
...result in the corresponding page table entry, complex interaction with internal processor activity may not be incorrect. Performance Monitor IDLE_DURING_DIV (18h) Count May Not be Accurate Problem: Performance monitoring events that count the number of Changes. Note: This ... a return from SMM (System Management Mode), the CPU will be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Workaround: None identified. The corresponding data if sent out...
Specification Update
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Status: For the steppings affected, see the Summary Tables of Changes. 42 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Under some circumstances, when STPCLK# becomes active, the BTS (Branch ..., see the Summary Tables of WB and WT memory types may cause the processor to perform incorrect operations leading to contain a workaround for this erratum with a complex sequence of STPCLK# assertions. Intel has not observed this erratum. Problem: STPCLK# is possible for the BIOS to...
Status: For the steppings affected, see the Summary Tables of Changes. 42 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Under some circumstances, when STPCLK# becomes active, the BTS (Branch ..., see the Summary Tables of WB and WT memory types may cause the processor to perform incorrect operations leading to contain a workaround for this erratum with a complex sequence of STPCLK# assertions. Intel has not observed this erratum. Problem: STPCLK# is possible for the BIOS to...
Specification Update
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... For String Operations in the Software Developers Manual section "Out-of Changes. Problem: Under certain conditions as described in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as opposed to 248 May Terminate Early Problem: In 64-bit Mode CMPSB, LODSB, or SCASB ...the case when the general detect enable flag (GD) bit is set, the observed behavior is that will now always be generated. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 43 Specification Update
... For String Operations in the Software Developers Manual section "Out-of Changes. Problem: Under certain conditions as described in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as opposed to 248 May Terminate Early Problem: In 64-bit Mode CMPSB, LODSB, or SCASB ...the case when the general detect enable flag (GD) bit is set, the observed behavior is that will now always be generated. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 43 Specification Update