Specification Update
Page 13
... Event AI72 X X X X Fixed PEBS Buffer Overflow Status Will Not be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update AI60 X X X X X No Fix MOV To/From Debug Registers Causes Debug...with EFLAGS.VM Set May Result in Unpredictable System Behavior AI65 X X X X X No Fix A Thermal Interrupt is Not Generated when the Current Temperature is Invalid AI66 X X X X Fixed VMLAUNCH/VMRESUME May Not Fail when VMCS is Set AI73 X X X X X No Fix The ...
... Event AI72 X X X X Fixed PEBS Buffer Overflow Status Will Not be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update AI60 X X X X X No Fix MOV To/From Debug Registers Causes Debug...with EFLAGS.VM Set May Result in Unpredictable System Behavior AI65 X X X X X No Fix A Thermal Interrupt is Not Generated when the Current Temperature is Invalid AI66 X X X X Fixed VMLAUNCH/VMRESUME May Not Fail when VMCS is Set AI73 X X X X X No Fix The ...
Specification Update
Page 46
...the IRET instruction even though alignment checks were disabled at the start of Changes. 46 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Status: For the steppings affected, see the Summary ... an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Workaround: None identified. Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is Invalid Problem: When the DTS (Digital...
...the IRET instruction even though alignment checks were disabled at the start of Changes. 46 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Status: For the steppings affected, see the Summary ... an interrupt and logs the event (IA32_THERM_STATUS MSR (019Ch) bits [9,7]). Workaround: None identified. Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is Invalid Problem: When the DTS (Digital...