Specification Update
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... Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequence Specification Update - Current characterized errata are documented in the 775-land LGA Package supporting Intel® 64Φ Architecture, Intel® Virtualization Technology± and Intel® Trusted Execution Technologyŧ December 2010 Notice: The Intel® CoreTM2 Extreme and Intel® CoreTM2 Duo desktop processor may contain design defects or errors known...
... Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequence Specification Update - Current characterized errata are documented in the 775-land LGA Package supporting Intel® 64Φ Architecture, Intel® Virtualization Technology± and Intel® Trusted Execution Technologyŧ December 2010 Notice: The Intel® CoreTM2 Extreme and Intel® CoreTM2 Duo desktop processor may contain design defects or errors known...
Specification Update
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... rely on your product order. Φ Intel® 64 requires a computer system with Execute Disable Bit capability and a supporting operating system. Check with Intel® Virtualization Technology, an Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor. Contact your local Intel sales office or your distributor to contain a TPMv1...
... rely on your product order. Φ Intel® 64 requires a computer system with Execute Disable Bit capability and a supporting operating system. Check with Intel® Virtualization Technology, an Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other Intel Trusted Execution Technology compatible measured virtual machine monitor. Contact your local Intel sales office or your distributor to contain a TPMv1...
Specification Update
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...Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI100 • Added Erratum AI101-AI104 • Updated Erratum AI33 in Summary table of changes • Added processor number E6320, E6420 and E4400 information Date July 2006 Out of the Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence Specification Update • Updated... Specification change AI1 • Updated Erratum AI46 and AI53 • Replaced Erratum AI10 with a new ...
...Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI100 • Added Erratum AI101-AI104 • Updated Erratum AI33 in Summary table of changes • Added processor number E6320, E6420 and E4400 information Date July 2006 Out of the Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence Specification Update • Updated... Specification change AI1 • Updated Erratum AI46 and AI53 • Replaced Erratum AI10 with a new ...
Specification Update
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... Mar 3rd 2008 May 2008 December 8th, 2010 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5 Specification Update AI23, AI38 - AI57, AI61, AI66, AI69, AI72, AI75, AI79, AI91, AI92, AI94, AI101, AI109 • Added processor number E4600 information • Added Erratum AI124 • Updated Plan status for errata AI20, AI24, AI31...
... Mar 3rd 2008 May 2008 December 8th, 2010 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5 Specification Update AI23, AI38 - AI57, AI61, AI66, AI69, AI72, AI75, AI79, AI91, AI92, AI94, AI101, AI109 • Added processor number E4600 information • Added Erratum AI124 • Updated Plan status for errata AI20, AI24, AI31...
Specification Update
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... Developer's Manual Volume 2B: Instruction Set Reference Manual, N-Z Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide Document Location http://www.intel.com/product s/processor/manuals/index.h tm 6 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update It is...
... Developer's Manual Volume 2B: Instruction Set Reference Manual, N-Z Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide Document Location http://www.intel.com/product s/processor/manuals/index.h tm 6 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update It is...
Specification Update
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... software designed to be incorporated in the specification update throughout the product's lifecycle, or until a particular stepping is no longer commercially available. These clarifications will be taken to identify products. Products are modifications to the appropriate product specification or user documentation (datasheets, manuals, etc.). § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
... software designed to be incorporated in the specification update throughout the product's lifecycle, or until a particular stepping is no longer commercially available. These clarifications will be taken to identify products. Products are modifications to the appropriate product specification or user documentation (datasheets, manuals, etc.). § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence...
Specification Update
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... to fix this stepping. (No mark) or (Blank Box): This erratum is either new or modified from the previous version of the document. 8 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Summary Tables of Changes Summary Tables of Changes The following notations: Codes Used in Summary Table Stepping X: Erratum, Specification Change or Clarification...
... to fix this stepping. (No mark) or (Blank Box): This erratum is either new or modified from the previous version of the document. 8 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Summary Tables of Changes Summary Tables of Changes The following notations: Codes Used in Summary Table Stepping X: Erratum, Specification Change or Clarification...
Specification Update
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... Dual-Core Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Hyper...
... Dual-Core Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel ® Xeon® processor Mobile Intel® Pentium® 4 processor supporting Hyper...
Specification Update
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...-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process Quad-Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor QX9775Δ Intel® Atom™ processor Z5xx series The Specification Updates for the Pentium® processor, Pentium® Pro processor, and other Intel products do not use...
...-Core Intel® Xeon® processor 5400 series Dual-Core Intel® Xeon® processor 5200 series Intel® Core™2 Duo Processor and Intel® Core™2 Extreme Processor on 45-nm Process Quad-Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor QX9775Δ Intel® Atom™ processor Z5xx series The Specification Updates for the Pentium® processor, Pentium® Pro processor, and other Intel products do not use...
Specification Update
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... Mode AI29 X X X X X No Fix #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When Execute Disable Bit is Not Supported AI30 X X Fixed (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
... Mode AI29 X X X X X No Fix #GP Fault is Not Generated on Writing IA32_MISC_ENABLE [34] When Execute Disable Bit is Not Supported AI30 X X Fixed (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
Specification Update
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... M0 G0 Plan ERRATA AI31 X X X X Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect AI33 X X X Fixed Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results MSRs Actual Frequency Clock...
... M0 G0 Plan ERRATA AI31 X X X X Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect AI33 X X X Fixed Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction Execution Results MSRs Actual Frequency Clock...
Specification Update
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... the Current Temperature is Invalid AI66 X X X X Fixed VMLAUNCH/VMRESUME May Not Fail when VMCS is Set AI73 X X X X X No Fix The BS Flag in 64-bit Mode AI64 X X X X X No Fix Returning to Real Mode from SMM with Inconsistent Memory Types may use an Incorrect Data Size or...AI63 X X X X X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in DR6 May be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update
... the Current Temperature is Invalid AI66 X X X X Fixed VMLAUNCH/VMRESUME May Not Fail when VMCS is Set AI73 X X X X X No Fix The BS Flag in 64-bit Mode AI64 X X X X X No Fix Returning to Real Mode from SMM with Inconsistent Memory Types may use an Incorrect Data Size or...AI63 X X X X X No Fix LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in DR6 May be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update
Specification Update
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...-Stepping on Branches Mode, the BS Bit in the Pending-Debug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM-Exit on a MOV to CR8 Instruction AI76 X X X X X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code ...Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions AI95 X X X X Fixed The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
...-Stepping on Branches Mode, the BS Bit in the Pending-Debug-Exceptions Field of the Guest State Area will be Incorrectly Set by VM-Exit on a MOV to CR8 Instruction AI76 X X X X X No Fix B0-B3 Bits in DR6 May Not be Properly Cleared After Code ...Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions AI95 X X X X Fixed The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
Specification Update
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... 7, 8, 9, 10, 11, 12, 13, 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 21 Specification Update Intel® Core™2 Duo Desktop Processor 2M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9SA B2 2M 06F6h E6300 SL9S9 B2 2M 06F6h E6400...Core/Bus 1.86 GHz / 1066 MHz 2.13 GHz / 1066 MHz 1.80 GHz / 800 MHz 2.00 GHz / 800 MHz 1.86 GHz / 1066 MHz 2.13 GHz / 1066 MHz 2.00 GHz / 800 MHz 2.20 GHz / 800 MHz 2.40 GHz / 800 MHz 2.60 GHz...
... 7, 8, 9, 10, 11, 12, 13, 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 21 Specification Update Intel® Core™2 Duo Desktop Processor 2M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9SA B2 2M 06F6h E6300 SL9S9 B2 2M 06F6h E6400...Core/Bus 1.86 GHz / 1066 MHz 2.13 GHz / 1066 MHz 1.80 GHz / 800 MHz 2.00 GHz / 800 MHz 1.86 GHz / 1066 MHz 2.13 GHz / 1066 MHz 2.00 GHz / 800 MHz 2.20 GHz / 800 MHz 2.40 GHz / 800 MHz 2.60 GHz...
Specification Update
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Intel® Core™2 Extreme Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9S5 B2 4M 06F6h X6800 Speed Core/Bus 2.93 GHz / 1066 MHz Package 775-land LGA Notes 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 22 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Intel® Core™2 Duo Desktop Processor 4M SKU Identification Information S-Spec SLAA5 SLA9X...
Intel® Core™2 Extreme Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9S5 B2 4M 06F6h X6800 Speed Core/Bus 2.93 GHz / 1066 MHz Package 775-land LGA Notes 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 22 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Intel® Core™2 Duo Desktop Processor 4M SKU Identification Information S-Spec SLAA5 SLA9X...
Specification Update
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...-bit L2 ECC errors. LOCK# Asserted During a Special Cycle Shutdown Transaction May Unexpectedly De-assert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during shutdown. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 23 Specification Update...
...-bit L2 ECC errors. LOCK# Asserted During a Special Cycle Shutdown Transaction May Unexpectedly De-assert Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is received during shutdown. Status: For the steppings affected, see the Summary Tables of Changes. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 23 Specification Update...
Specification Update
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... Problem: With respect to the retirement of Changes. Implication: When this example the processor may delay their service. Status: For the steppings affected, see the Summary Tables of the single-step debug exception (#DB) may take effect before updating the DTS threshold value. 26 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
... Problem: With respect to the retirement of Changes. Implication: When this example the processor may delay their service. Status: For the steppings affected, see the Summary Tables of the single-step debug exception (#DB) may take effect before updating the DTS threshold value. 26 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update...
Specification Update
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... Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 37 Specification Update Errata AI39. Workaround: It is possible for the BIOS to processor livelock. Cache Data Access Request from Core 1 results in the L1 Data Cache of Control Register CR0 to disable alignment checking. Implication: Due to this erratum, the processor may cause incorrect data to be set . • An FXSAVE instruction...
... Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 37 Specification Update Errata AI39. Workaround: It is possible for the BIOS to processor livelock. Cache Data Access Request from Core 1 results in the L1 Data Cache of Control Register CR0 to disable alignment checking. Implication: Due to this erratum, the processor may cause incorrect data to be set . • An FXSAVE instruction...
Specification Update
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... from SMM (System Management Mode), the CPU will also be used . Implication: The counter may cause unpredictable system behavior. Values for BIOS to the same non-dirty page or explicitly sets the dirty bit in progress may be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI46.
... from SMM (System Management Mode), the CPU will also be used . Implication: The counter may cause unpredictable system behavior. Values for BIOS to the same non-dirty page or explicitly sets the dirty bit in progress may be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI46.
Specification Update
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... second load will operate correctly. Implication: Software that uses non-temporal data without proper serialization before accessing the non-temporal data may Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 51 Specification Update Implication: Software that conforms to 1, a MOV instruction from CR8 with a 16 bit operand size (REX.W =0 and 66H prefix) will only...
... second load will operate correctly. Implication: Software that uses non-temporal data without proper serialization before accessing the non-temporal data may Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 51 Specification Update Implication: Software that conforms to 1, a MOV instruction from CR8 with a 16 bit operand size (REX.W =0 and 66H prefix) will only...
