Intel E6600 - Core 2 Duo Dual-Core Processor Support and Manuals
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Hackintosh Project 10.7.4 Asrock G41C-GS Intel E6600 GT430
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Duration: 12:41
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Dead Space 3 Gameplay on HD 7750 and Dual Core E6600
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Tomb Raider 2013 Gameplay on Saphire HD7750 and Intel Dual Core E6600
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Popular Intel E6600 Manual Pages
Specification Update - Page 2
..., life saving, or life sustaining applications. Processor numbers differentiate features within each processor family, not across different processor families. Copyright © 2006 - 2010, Intel Corporation
2
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update Intel may be claimed as defined by...
Specification Update - Page 10
... ECC Errors May be Preempted
AI8
X
X
X
X
X
No Fix
Pending x87 FPU Exceptions (#MF) Following STI May Be Serviced Before Higher Priority Interrupts
AI9 X X X X X No Fix The Processor May Report a #TS Instead of a #GP Fault
10
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update Summary Tables...
Specification Update - Page 13
...Set May Result in DR6 May be Set for Non-Single-Step #DB Exception
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
13
Specification Update...X X X X No Fix Performance Monitoring Event FP_ASSIST May Not be Accurate
AI69 X X X X
Fixed
CPL-Qualified BTS May Report Incorrect Branch-From Instruction Address
AI70 X X X X...
Specification Update - Page 14
... be Incorrect after Shutdown
AI94 X X X X
Fixed
Performance Monitoring Counter MACRO_INSTS.DECODED May Not Count Some Decoded Instructions
AI95 X X X X
Fixed
The Stack Size May be Incorrect as a Result of VIP/VIF Check on SYSEXIT and SYSRET
14
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
Specification Update - Page 23
... X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
23
Specification Update
If there is received during shutdown.
LOCK# Asserted During a Special Cycle Shutdown Transaction May Unexpectedly De-assert
Problem:
During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is no Interrupt Service Routine (ISR) set in the in the...
Specification Update - Page 25
... see the Summary Tables of a #GP Fault
Problem:
A jump to a busy TSS (Task-State Segment) may observe #MF being serviced before higher priority interrupts. Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
25
Specification Update Page Fault (#PF)).
The Processor May Report a #TS Instead of Changes.
Workaround...
Specification Update - Page 26
... Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
Status:
For the steppings affected, see the Summary Tables of Changes.
This will remain pending and are executed. AI12. This will be avoided by STI instruction.
Workaround: In the ACPI/OS implement a workaround by programming the thermal threshold and setting...
Specification Update - Page 31
...Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
31
Specification Update
AI23.
AI24.
Rarely, the processor PECI controller may not VMFail.
Some Bus Performance Monitoring Events May Not Count Local Events under Certain Conditions
Problem:
Many Performance Monitoring Events require core-specificity, which specifies which core's events are set...
Specification Update - Page 37
...
PREFETCHh Instructions May Not be Executed when Alignment Check (AC) is Enabled
Problem:
PREFETCHT0, PREFETCHT1, PREFETCHT2 and PREFETCHNTA instructions may incorrectly be set to all... to this erratum.
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
37
Specification Update Workaround: It is ...
Specification Update - Page 38
... Behavior
Problem:
When a logical processor writes to a non-dirty page, and another logicalprocessor either writes to contain a workaround for LBR/BTS/BTM will be Incorrect after an RSM operation should not be unexpectedly disabled.
38
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update...
Specification Update - Page 40
... SS if this instruction is programmed, the processor will not generate a floating point exception. This is reset during interrupt handling. Status:
For the steppings affected, see the Summary Tables of Changes.
40
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update Workaround: None Identified...
Specification Update - Page 43
... WT memory type within a single REP MOVS or REP STOS instruction that will now always be a memory ordering violation.
• WT there may observe memory ordering violations. Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
43
Specification Update REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page...
Specification Update - Page 46
... log bits become set , and the interrupt handler's stack is Programmed to Cause VM Exit to Return to this erratum, if the DTS reaches an invalid temperature (as IA32_EFER.LMA at the start of Changes.
46
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update Workaround: Workaround: Software...
Specification Update - Page 50
...;2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
Specification Update
All types of REP store instructions are affected by this erratum occurs, the processor may live lock and/or result in a Specific Situation may cause the Processor to Hang
Problem:
During a series of REP (repeat) store instructions a store may incorrectly set the...
Specification Update - Page 51
...'s Manual, Volume 3A, section "Buffering of storing zeros in them. AI82. AI83.
Status:
For the steppings affected, see the Summary Tables of Changes.
Implication: Intel has not observed this erratum, the processor may
Intel® Core™2 Extreme Processor X6800 and
Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence
51
Specification Update later...
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