Specification Update
Page 9
...; Duo processor and Intel® Core™ Solo processor on 65nm process Dual-Core Intel® Xeon® processor LV Dual-Core Intel® Xeon® processor 5100 series Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor technology Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 sequence Quad-Core Intel® Xeon® processor 5300 series Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor...
...; Duo processor and Intel® Core™ Solo processor on 65nm process Dual-Core Intel® Xeon® processor LV Dual-Core Intel® Xeon® processor 5100 series Intel® Core™2 Duo/Solo processor for Intel® Centrino® Duo processor technology Intel® Core™2 Extreme processor X6800 and Intel® Core™2 Duo desktop processor E6000 and E4000 sequence Quad-Core Intel® Xeon® processor 5300 series Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor...
Specification Update
Page 10
...® dual-core processor Quad-Core Intel® Xeon® processor 3200 series Dual-Core Intel® Xeon® processor 3000 series Intel® Pentium® dual-core desktop processor E2000 sequence Intel® Celeron® processor 500 series Intel® Xeon® processor 7200, 7300 series Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000 series Intel® Core™ 2 Duo processor E8000 series Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel®...
...® dual-core processor Quad-Core Intel® Xeon® processor 3200 series Dual-Core Intel® Xeon® processor 3000 series Intel® Pentium® dual-core desktop processor E2000 sequence Intel® Celeron® processor 500 series Intel® Xeon® processor 7200, 7300 series Intel® Core™2 Extreme processor QX9650 and Intel® Core™2 Quad processor Q9000 series Intel® Core™ 2 Duo processor E8000 series Quad-Core Intel® Xeon® processor 5400 series Dual-Core Intel®...
Specification Update
Page 11
...State from SMRAM AI22 X X X X Fixed Sequential Code Fetch to Non-canonical Address May have Non-deterministic Results AI23 X X X X Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field AI24 X X X X X No Fix The PECI Controller Resets to the ... X X Fixed (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
...State from SMRAM AI22 X X X X Fixed Sequential Code Fetch to Non-canonical Address May have Non-deterministic Results AI23 X X X X Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field AI24 X X X X X No Fix The PECI Controller Resets to the ... X X Fixed (E)CX May Get Incorrectly Updated When Performing Fast String REP MOVS or Fast String REP STOS With Large Data Structures Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
Specification Update
Page 31
...Performance Monitoring Events require core-specificity, which specifies which core's events are set to an incoming message immediately after reset and will be counted (local core, other core or both cores). Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence... not disregard an incoming message that the message was intended for the first rising edge. AI23. Due to Activate Dual-monitor Treatment of Changes. The PECI Controller Resets to the Idle State Problem: After reset, the Platform Environment Control...
...Performance Monitoring Events require core-specificity, which specifies which core's events are set to an incoming message immediately after reset and will be counted (local core, other core or both cores). Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence... not disregard an incoming message that the message was intended for the first rising edge. AI23. Due to Activate Dual-monitor Treatment of Changes. The PECI Controller Resets to the Idle State Problem: After reset, the Platform Environment Control...
Specification Update
Page 62
...may be incorrect for this erratum with any commercially available software. Intel has not observed this erratum. 62 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI114. Workaround: It is ... GETSEC[WAKEUP] Instruction May Result in a Processor Hang In dual core processor systems supporting Intel® Trusted Execution Technology, a processor hang or unpredictable system behavior may occur if the ILP (Initiating Logical Processor) executes GETSEC[WAKEUP] and then executes GETSEC...
...may be incorrect for this erratum with any commercially available software. Intel has not observed this erratum. 62 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI114. Workaround: It is ... GETSEC[WAKEUP] Instruction May Result in a Processor Hang In dual core processor systems supporting Intel® Trusted Execution Technology, a processor hang or unpredictable system behavior may occur if the ILP (Initiating Logical Processor) executes GETSEC[WAKEUP] and then executes GETSEC...