Product Specification
Page 27
...GPO GPIO:R00h[16]=1 (GPIO) GPIO:R0Ch[16] (GPIO:R04h[16] always = 0) Pin Description NC N/A TTL Driver Output GPO GPIO:R00h[17]=1 (GPIO) GPIO:R0Ch[17] (GPIO:R04h[16] always = 0) TTL Driver Output GPO GPO GPO GPIO:R18h[18:19] for CPU 1 & 2 GPI14 ~ GPI15 GPO16 / N/C GNTA# (Core...:R04h[12] always = 1) GPIO:R2Ch[12]=0 (Active High) (GPIO:R04h[13] always = 1) GPIO:R2Ch[13]=1 (Active Low) Data. Intel® Server Board SE7505VB2 Functional Architecture Pin Name (Powe Well) Used As GPI12 (Resume) GPI13 (Resume) Overtemperature shutdown for Blinking GPIO:R0Ch[18:19] (GPIO:R04h[18:...
...GPO GPIO:R00h[16]=1 (GPIO) GPIO:R0Ch[16] (GPIO:R04h[16] always = 0) Pin Description NC N/A TTL Driver Output GPO GPIO:R00h[17]=1 (GPIO) GPIO:R0Ch[17] (GPIO:R04h[16] always = 0) TTL Driver Output GPO GPO GPO GPIO:R18h[18:19] for CPU 1 & 2 GPI14 ~ GPI15 GPO16 / N/C GNTA# (Core...:R04h[12] always = 1) GPIO:R2Ch[12]=0 (Active High) (GPIO:R04h[13] always = 1) GPIO:R2Ch[13]=1 (Active Low) Data. Intel® Server Board SE7505VB2 Functional Architecture Pin Name (Powe Well) Used As GPI12 (Resume) GPI13 (Resume) Overtemperature shutdown for Blinking GPIO:R0Ch[18:19] (GPIO:R04h[18:...
Product Specification
Page 31
Clock synthesizer/driver circuitry on the board. Revision 1.2 31 Intel part number C32194-002 For Processor 0, Processor 1, Debug Port and MCH. 66 MHz at 3.3 V logic levels: For MCH, ICH4, AGP, and P64H2 48 MHz at 3.... baseboard generates clock frequencies and voltage levels as required, including the following: 100 MHz at 3.3 V logic levels. Clock Generation and Distribution All buses on the Intel Server Board SE7505VB2 operate using synchronous clocks. Intel® Server Board SE7505VB2 Clock Generation and Distribution 4.
Clock synthesizer/driver circuitry on the board. Revision 1.2 31 Intel part number C32194-002 For Processor 0, Processor 1, Debug Port and MCH. 66 MHz at 3.3 V logic levels: For MCH, ICH4, AGP, and P64H2 48 MHz at 3.... baseboard generates clock frequencies and voltage levels as required, including the following: 100 MHz at 3.3 V logic levels. Clock Generation and Distribution All buses on the Intel Server Board SE7505VB2 operate using synchronous clocks. Intel® Server Board SE7505VB2 Clock Generation and Distribution 4.
Product Specification
Page 36
...PCI graphics accelerator, along with 8 MB of the system, in the standard ATX I /O Subsystem Intel® Server Board SE7505VB2 The baseboard ships with up to support dual monitor mode when an off -board video adapter is detected. It supports both CRT and LCD monitors with the Silicon Image controller set...transfer rate of Drives 2 2 RAID 0 configurations are primarily used for the ATA mode/RAID mode utility to the other. If the RAID drivers were loaded and a Clear CMOS operation was executed, but the device was chosen over a BIOS F2 setup switch to allow the controller settings...
...PCI graphics accelerator, along with 8 MB of the system, in the standard ATX I /O Subsystem Intel® Server Board SE7505VB2 The baseboard ships with up to support dual monitor mode when an off -board video adapter is detected. It supports both CRT and LCD monitors with the Silicon Image controller set...transfer rate of Drives 2 2 RAID 0 configurations are primarily used for the ATA mode/RAID mode utility to the other. If the RAID drivers were loaded and a Clear CMOS operation was executed, but the device was chosen over a BIOS F2 setup switch to allow the controller settings...
Product Specification
Page 49
...is capable of these events. The reset button will force an NMI to shutdown the system. Table 19. The operating system or a driver must clear any ) the system transitions to the power supply. The sIO provides ONSTL# signal to . Supported Wake Events Wake Event ...system and determines what sleep state (if any pending wake up sources based on whether or not the operating system supports ACPI. Intel® Server Board SE7505VB2 SE7505VB2 ACPI Implementation The power button input (SW2#) provides PWRBTN_IN signal to an ON state. Since the processors are defined in the...
...is capable of these events. The reset button will force an NMI to shutdown the system. Table 19. The operating system or a driver must clear any ) the system transitions to the power supply. The sIO provides ONSTL# signal to . Supported Wake Events Wake Event ...system and determines what sleep state (if any pending wake up sources based on whether or not the operating system supports ACPI. Intel® Server Board SE7505VB2 SE7505VB2 ACPI Implementation The power button input (SW2#) provides PWRBTN_IN signal to an ON state. Since the processors are defined in the...