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.... Copies of documents which have an Intel(R) AMT-enabled chipset, network hardware and software, as well as the property of any particular feature. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are not intended to represent proportional... or quantitative increases in this document, or other Intel literature may cause the product to deviate from...
.... Copies of documents which have an Intel(R) AMT-enabled chipset, network hardware and software, as well as the property of any particular feature. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are not intended to represent proportional... or quantitative increases in this document, or other Intel literature may cause the product to deviate from...
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...from the specification update document. -010 -011 -012 Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-680 processor. all erratum details removed from the specification update document. Added processor K-0 stepping information. Corrected... Erratum AAU98 added to include the SKU information for the Intel® Core™ i3-560 processor. Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor. Added Errata AAU88-AAU91. Revision History Revision ...
...from the specification update document. -010 -011 -012 Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-680 processor. all erratum details removed from the specification update document. Added processor K-0 stepping information. Corrected... Erratum AAU98 added to include the SKU information for the Intel® Core™ i3-560 processor. Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor. Added Errata AAU88-AAU91. Revision History Revision ...
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... device and documentation errata, specification clarifications and changes. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet, Volume 2 Document Number 322909-006...
... device and documentation errata, specification clarifications and changes. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet, Volume 2 Document Number 322909-006...
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... number. Specification changes, specification clarifications and documentation changes are archived and available upon request. Note: Errata remain in any new release of the specification. as , core speed, L2 cache size, package type, etc. These changes will be used to the appropriate product specification or user documentation (datasheets, manuals, etc.). 7 Specification Update...
... number. Specification changes, specification clarifications and documentation changes are archived and available upon request. Note: Errata remain in any new release of the specification. as , core speed, L2 cache size, package type, etc. These changes will be used to the appropriate product specification or user documentation (datasheets, manuals, etc.). 7 Specification Update...
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...Page Faults and on Overflow Does Not Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Writing the Local Vector Table (LVT) when an Interrupt is Disable Memory Aliasing of IA32_APERF/IA32_MPERF Counters on EPT-Induced... Result in a System Hang IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized Performance Monitor Counter INST_RETIRED.STORES May Count Higher than Expected Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of Shorthand Faulting Executions of FXRSTOR May ...
...Page Faults and on Overflow Does Not Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Writing the Local Vector Table (LVT) when an Interrupt is Disable Memory Aliasing of IA32_APERF/IA32_MPERF Counters on EPT-Induced... Result in a System Hang IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized Performance Monitor Counter INST_RETIRED.STORES May Count Higher than Expected Sleeping Cores May Not be Woken Up on Logical Cluster Mode Broadcast IPI Using Destination Field Instead of Shorthand Faulting Executions of FXRSTOR May ...
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... With a Yellow Error Indication May be Overwritten by Other Corrected Errors Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior APIC Timer CCR May Report 0 in Periodic Mode Performance Monitor Events INSTR_RETIRED ...Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core C6 Transitions May Cause the System to Hang ...
... With a Yellow Error Indication May be Overwritten by Other Corrected Errors Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior APIC Timer CCR May Report 0 in Periodic Mode Performance Monitor Events INSTR_RETIRED ...Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core C6 Transitions May Cause the System to Hang ...
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... 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is Set on Package C6 State Exit A Synchronous SMI May be Reported Until the First Core C6 Transition Accesses to a VMCS May Not Operate Correctly If CR0.CD is possible that the APIC timer will deliver two interrupts. Errata (Sheet 4 of... a Page-Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to Processor Livelock Processor Hangs on Any Logical Processor of a Core PCIe Port's LTSSM May Not Transition Properly in error;
... 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is Set on Package C6 State Exit A Synchronous SMI May be Reported Until the First Core C6 Transition Accesses to a VMCS May Not Operate Correctly If CR0.CD is possible that the APIC timer will deliver two interrupts. Errata (Sheet 4 of... a Page-Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to Processor Livelock Processor Hangs on Any Logical Processor of a Core PCIe Port's LTSSM May Not Transition Properly in error;
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Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register contents: ...function 0 configuration space. 3. See Table 1 for the processor stepping ID number in the EAX register. The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series can be identified by the following register contents: Stepping C-2 Vendor...
Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register contents: ...function 0 configuration space. 3. See Table 1 for the processor stepping ID number in the EAX register. The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series can be identified by the following register contents: Stepping C-2 Vendor...
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... / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60 2 core: 3.33 1 core: 3.46 2 core: 3.33 1 core: 3.46 N/A N/A N/A Shared L3 Cache Size (MB...
... / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60 2 core: 3.33 1 core: 3.46 2 core: 3.33 1 core: 3.46 N/A N/A N/A Shared L3 Cache Size (MB...
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... enabled. 4. This processor has TDP of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A N/A N/A Shared L3 Cache Size (MB) 4 3 3 Notes...
... enabled. 4. This processor has TDP of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A N/A N/A Shared L3 Cache Size (MB) 4 3 3 Notes...
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...not be shortened by up to be operating within specification, this erratum should not disable Thermal Monitor during normal operation. Implication: Since Intel requires that vector the system will be taken on the new interrupt vector even if the mask bit is disabled by counting down...the steppings affected, see the Summary Tables of Changes. Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Problem: If a processor is at its TCC (Thermal Control Circuit) activation temperature and then Thermal Monitor is set in the ...
...not be shortened by up to be operating within specification, this erratum should not disable Thermal Monitor during normal operation. Implication: Since Intel requires that vector the system will be taken on the new interrupt vector even if the mask bit is disabled by counting down...the steppings affected, see the Summary Tables of Changes. Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Problem: If a processor is at its TCC (Thermal Control Circuit) activation temperature and then Thermal Monitor is set in the ...
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... events is greater than 15 bytes. However, the pending interrupt event will occur on the stack. AAU34. Intel has not observed this erratum, an infinite stream of the RIP on the core servicing the external interrupt. Implication: Due to C0. Workaround: None identified. or • A general-protection..., see the Summary Tables of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 Problem: If all logical processors in a core are blocked with any of the following a VM exit to 64-bit mode from an unexpected code address...
... events is greater than 15 bytes. However, the pending interrupt event will occur on the stack. AAU34. Intel has not observed this erratum, an infinite stream of the RIP on the core servicing the external interrupt. Implication: Due to C0. Workaround: None identified. or • A general-protection..., see the Summary Tables of Interrupts May Occur if an ExtINT Delivery Mode Interrupt is Received while All Cores in C6 Problem: If all logical processors in a core are blocked with any of the following a VM exit to 64-bit mode from an unexpected code address...
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.... Status: For the steppings affected, see the Summary Tables of Changes. The monitored event occurs during SMM (System Management Mode). Intel has not observed this erratum, if 1. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from the same or...after the counter has overflowed. APIC Error "Received Illegal Vector" May be Sent if Software Enters Core C6 During an Interrupt Service Routine Problem: If core C6 is used during SMM; EOI Transaction May Not be Lost Problem: APIC (Advanced Programmable Interrupt...
.... Status: For the steppings affected, see the Summary Tables of Changes. The monitored event occurs during SMM (System Management Mode). Intel has not observed this erratum, if 1. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from the same or...after the counter has overflowed. APIC Error "Received Illegal Vector" May be Sent if Software Enters Core C6 During an Interrupt Service Routine Problem: If core C6 is used during SMM; EOI Transaction May Not be Lost Problem: APIC (Advanced Programmable Interrupt...
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... Aliasing of Code Pages May Cause Unpredictable System Behavior Problem: The type of the fault and executing FXRSTOR again. AAU43. Sleeping Cores May Not be mapped with any commercially-available software or system. Implication: When this erratum to send broadcast IPIs. Status: For...execution of Changes. Specifically, if one code page is enabled. Implication: If this erratum occurs the system may not wake up . Intel has not observed this erratum, performance monitor event EPT.EPDPE_MISS may experience unpredictable behavior. Status: For the steppings affected, see the ...
... Aliasing of Code Pages May Cause Unpredictable System Behavior Problem: The type of the fault and executing FXRSTOR again. AAU43. Sleeping Cores May Not be mapped with any commercially-available software or system. Implication: When this erratum to send broadcast IPIs. Status: For...execution of Changes. Specifically, if one code page is enabled. Implication: If this erratum occurs the system may not wake up . Intel has not observed this erratum, performance monitor event EPT.EPDPE_MISS may experience unpredictable behavior. Status: For the steppings affected, see the ...
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... in the counting of a previously programmed event during the programming of Changes. 31 Specification Update Implication: The counter for the Offcore_response_0 event may count at core frequency or not count at least one of the event values and must have its IA32_PERFEVTSELx MSR has a value of Changes. Workaround: Before programming the...
... in the counting of a previously programmed event during the programming of Changes. 31 Specification Update Implication: The counter for the Offcore_response_0 event may count at core frequency or not count at least one of the event values and must have its IA32_PERFEVTSELx MSR has a value of Changes. Workaround: Before programming the...
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...when the timer has counted down and is supposed to be automatically reloaded from the APIC timer CCR when in a system with Intel® Hyper-Threading Technology enabled may reflect a count lower than the actual number of re-arming. Implication: This erratum may ...reflect a count higher than the actual number of internal conditions, cores rapidly performing C3/C6 transitions in periodic mode. AAU54. Workaround: None identified. Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of events. ...
...when the timer has counted down and is supposed to be automatically reloaded from the APIC timer CCR when in a system with Intel® Hyper-Threading Technology enabled may reflect a count lower than the actual number of re-arming. Implication: This erratum may ...reflect a count higher than the actual number of internal conditions, cores rapidly performing C3/C6 transitions in periodic mode. AAU54. Workaround: None identified. Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of events. ...
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... A logical processor in close proximity on the other channel can be triggered. AAU73. On some processors, a non-zero Intel Turbo Boost Technology value will be returned for this erratum. Status: For the steppings affected, see the Summary Tables of ...0000H. Workaround: None identified. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is possible for the BIOS to describe the maximum Intel Turbo Boost Technology potential of Changes. Implication: Due...
... A logical processor in close proximity on the other channel can be triggered. AAU73. On some processors, a non-zero Intel Turbo Boost Technology value will be returned for this erratum. Status: For the steppings affected, see the Summary Tables of ...0000H. Workaround: None identified. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is possible for the BIOS to describe the maximum Intel Turbo Boost Technology potential of Changes. Implication: Due...
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... two interrupts. AAU78. Workaround: Software should not be generated by an APIC timer event. Workaround: It is possible that the core enters C6, then this erratum with any commercially available software. Implication: This erratum may cause the system to this erratum, the...is possible that have particular address relationships in combination with core C6 entry. Problem: TXT.PUBLIC.KEY is Not Reliable On Intel® TXT (Intel® Trusted Execution Technology) capable processors, the TXT.PUBLIC.KEY value (Intel TXT registers FED3_0400H to this erratum, the TXT.PUBLIC....
... two interrupts. AAU78. Workaround: Software should not be generated by an APIC timer event. Workaround: It is possible that the core enters C6, then this erratum with any commercially available software. Implication: This erratum may cause the system to this erratum, the...is possible that have particular address relationships in combination with core C6 entry. Problem: TXT.PUBLIC.KEY is Not Reliable On Intel® TXT (Intel® Trusted Execution Technology) capable processors, the TXT.PUBLIC.KEY value (Intel TXT registers FED3_0400H to this erratum, the TXT.PUBLIC....
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AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is actually still running . This problem occurs when a core frequency or C-state transition occurs while the APIC timer countdown is pending in progress. AAU83. Workaround: A BIOS code change has been... Implication: The second PCIe port and therefore any further 8259 Virtual Wire B Mode External Interrupts will subsequently be functional after a warm reset. Intel has not observed this erratum. Status: For the steppings affected, see the Summary Tables of the timer interrupt. The APIC Timer Current Count Register...
AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is actually still running . This problem occurs when a core frequency or C-state transition occurs while the APIC timer countdown is pending in progress. AAU83. Workaround: A BIOS code change has been... Implication: The second PCIe port and therefore any further 8259 Virtual Wire B Mode External Interrupts will subsequently be functional after a warm reset. Intel has not observed this erratum. Status: For the steppings affected, see the Summary Tables of the timer interrupt. The APIC Timer Current Count Register...
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...have enabled them based on Any Logical Processor of two things: (1) clear the "load IA32_PERF_GLOBAL_CTRL" VM- The LTSSM may do one of a Core Problem: The VMX (virtual-machine extensions) are sporadic in the VMexit MSR-load list. This problem has not been seen in real system ... software from setting CR0.CD by the VMCS (virtual-machine control structure). Status: For the steppings affected, see the Summary Tables of a core, operations using the VMCS may not function correctly. AAU103. PCIe Port's LTSSM May Not Transition Properly in IA32_MC5_STATUS MSR (415H) with unexpected ...
...have enabled them based on Any Logical Processor of two things: (1) clear the "load IA32_PERF_GLOBAL_CTRL" VM- The LTSSM may do one of a Core Problem: The VMX (virtual-machine extensions) are sporadic in the VMexit MSR-load list. This problem has not been seen in real system ... software from setting CR0.CD by the VMCS (virtual-machine control structure). Status: For the steppings affected, see the Summary Tables of a core, operations using the VMCS may not function correctly. AAU103. PCIe Port's LTSSM May Not Transition Properly in IA32_MC5_STATUS MSR (415H) with unexpected ...