Specifications
Page 2
... on hardware and software configurations and may be obtained by calling 1-800-5484725 or by visiting Intel's website at any features or instructions marked "reserved" or "undefined." For more information, see http://www.intel.com/info/hyperthreading. 64-bit computing on the specific hardware and software you use in medical, life saving, life sustaining...
... on hardware and software configurations and may be obtained by calling 1-800-5484725 or by visiting Intel's website at any features or instructions marked "reserved" or "undefined." For more information, see http://www.intel.com/info/hyperthreading. 64-bit computing on the specific hardware and software you use in medical, life saving, life sustaining...
Specifications
Page 9
... Not Be Signaled on Data Segment Limit Violation above 4-G Limit LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints MONITOR...
... Not Be Signaled on Data Segment Limit Violation above 4-G Limit LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode MCi_Status Overflow Bit May Be Incorrectly Set on a Single Instance of a DTLB Error Debug Exception Flags DR6.B0-B3 Flags May be Incorrect for Disabled Breakpoints MONITOR...
Specifications
Page 12
... Errors May be Delayed FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64bit Mode PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to 2.5GT/s PCI Express Cards May Not Train... Low Within tRFC(min) After a PD Exit Erratum AAU98 added to this specification Update in SMRAM State Save Area May Be Lost VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets 12 Specification Update
... Errors May be Delayed FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in 64bit Mode PCI Express x16 Port Links May Fail to Dynamically Switch From 5.0GT/s to 2.5GT/s PCI Express Cards May Not Train... Low Within tRFC(min) After a PD Exit Erratum AAU98 added to this specification Update in SMRAM State Save Area May Be Lost VM Entry to 64-Bit Mode May Fail if Bits 48 And 47 of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets 12 Specification Update
Specifications
Page 21
...lower canonical boundary (0x00007FFFFFFFFFFF) in the MCi_Status register. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should ensure that is greater than 15 bytes in length, a #GP is signaled when the instruction is... can only occur if redundant prefixes are resolved by MCA error code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in 64-bit mode, the LBR return registers will save a wrong return address with Bits 63 to 48 incorrectly sign extended to all 1's. Instructions of Changes....
...lower canonical boundary (0x00007FFFFFFFFFFF) in the MCi_Status register. LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should ensure that is greater than 15 bytes in length, a #GP is signaled when the instruction is... can only occur if redundant prefixes are resolved by MCA error code (bits [15:0]) appearing as binary value, 000x 0000 0001 0100, in 64-bit mode, the LBR return registers will save a wrong return address with Bits 63 to 48 incorrectly sign extended to all 1's. Instructions of Changes....
Specifications
Page 22
...CS segment register to protected mode, if an SMI (System Management Interrupt) occurs between enabling protected mode and the first FAR JMP. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1, in DR7 is disabled. AAU19. Implication: ... FAR JMP, the subsequent RSM (Resume from System Management Mode) may cause the lower two bits of Changes. Implication: The corruption of the bottom two bits of Changes. Intel has not observed this erratum occurs, the processor will have no impact unless software explicitly examines...
...CS segment register to protected mode, if an SMI (System Management Interrupt) occurs between enabling protected mode and the first FAR JMP. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1, in DR7 is disabled. AAU19. Implication: ... FAR JMP, the subsequent RSM (Resume from System Management Mode) may cause the lower two bits of Changes. Implication: The corruption of the bottom two bits of Changes. Intel has not observed this erratum occurs, the processor will have no impact unless software explicitly examines...
Specifications
Page 27
... bytes. Status: For the steppings affected, see the Summary Tables of Changes. However, the pending interrupt event will be generated by an xAPIC timer event. Intel has not observed this erratum. Implication: Due to 0: • A non-maskable interrupt (NMI); • A machine-check exception (#MC); •... delivery mode interrupt is pending in the xAPIC and interrupts are blocked with any of the following a VM exit to 64-bit mode from outside 64-bit mode, bits 63:32 of Changes. 27 Specification Update Implication: Due to this erratum, two interrupts may occur due to C0....
... bytes. Status: For the steppings affected, see the Summary Tables of Changes. However, the pending interrupt event will be generated by an xAPIC timer event. Intel has not observed this erratum. Implication: Due to 0: • A non-maskable interrupt (NMI); • A machine-check exception (#MC); •... delivery mode interrupt is pending in the xAPIC and interrupts are blocked with any of the following a VM exit to 64-bit mode from outside 64-bit mode, bits 63:32 of Changes. 27 Specification Update Implication: Due to this erratum, two interrupts may occur due to C0....
Specifications
Page 34
...and no page fault will occur due to "1" in a PML4E or PDPTE On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may ...of the linear address of a memory access encounters a PML4E or a PDPTE with PS set . BIST Results May be Generated When the PS bit is expected. Implication: Software may show a different value in EAX upon wakeup than before the #MF. AAU56. Problem: A Page Fault May...
...and no page fault will occur due to "1" in a PML4E or PDPTE On processors supporting Intel® 64 architecture, the PS bit (Page Size, bit 7) is executed while Enhanced Intel SpeedStep® Technology transitions, Intel® Turbo Boost Technology transitions, or Thermal Monitor events occur, the pending #MF may ...of the linear address of a memory access encounters a PML4E or a PDPTE with PS set . BIST Results May be Generated When the PS bit is expected. Implication: Software may show a different value in EAX upon wakeup than before the #MF. AAU56. Problem: A Page Fault May...
Specifications
Page 43
... x8 link width. If an 80bit FP access (load or store) uses a 32-bit address size in 64-bit Mode Problem: The FP (Floating Point) Data Operand Pointer is not a normal programming practice. Intel has not observed this erratum. 43 Specification Update Status: For the steppings affected, see ... Function 0; Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express CLB (Compliance Load Board) Cards used in a 64-bit operating system which may be taken to ensure that may only train to lose sync, eventually resulting in the Link Capabilities register (LCAP; No...
... x8 link width. If an 80bit FP access (load or store) uses a 32-bit address size in 64-bit Mode Problem: The FP (Floating Point) Data Operand Pointer is not a normal programming practice. Intel has not observed this erratum. 43 Specification Update Status: For the steppings affected, see ... Function 0; Implication: PCI Express x16 Graphics Cards used in normal operation and PCI Express CLB (Compliance Load Board) Cards used in a 64-bit operating system which may be taken to ensure that may only train to lose sync, eventually resulting in the Link Capabilities register (LCAP; No...
Specifications
Page 44
... X87 FSW (FPU Status Word) may instead load SS.B from that of bit 48. Due to this erratum. Intel has not observed this erratum with any value for bits [47:0] of Guest RIP Are Different Problem: VM entry to 64-bit mode should set to "1" by the processor to indicate a System Management Interrupt... this erratum, VM entry may be able to 0. Status: For the steppings affected, see the Summary Tables of I /O instruction or is executed in 64-bit mode with an immediate operand, an adjustment is possible for the BIOS to contain a workaround for this erratum, SMI handlers may fail if...
... X87 FSW (FPU Status Word) may instead load SS.B from that of bit 48. Due to this erratum. Intel has not observed this erratum with any value for bits [47:0] of Guest RIP Are Different Problem: VM entry to 64-bit mode should set to "1" by the processor to indicate a System Management Interrupt... this erratum, VM entry may be able to 0. Status: For the steppings affected, see the Summary Tables of I /O instruction or is executed in 64-bit mode with an immediate operand, an adjustment is possible for the BIOS to contain a workaround for this erratum, SMI handlers may fail if...