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... the Trusted Computing Group and specific software for some uses, certain computer system software enabled for some uses. The MLE could consist of new business processes. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are not intended to obtain the latest specifications and before placing your product order. Intel processor numbers are not intended for use . For more information including details...
... the Trusted Computing Group and specific software for some uses, certain computer system software enabled for some uses. The MLE could consist of new business processes. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are not intended to obtain the latest specifications and before placing your product order. Intel processor numbers are not intended for use . For more information including details...
Specifications
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... November 2010 January 2011 5 Specification Update Added processor K-0 stepping information. Added Errata AAU88-AAU91. AAU97 -007 -008 -009 Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor. Corrected Extended Model and Model Number register values in error, all erratum details removed from the specification update document. -010 -011 -012 Updated Processor Identification table to include the...
... November 2010 January 2011 5 Specification Update Added processor K-0 stepping information. Added Errata AAU88-AAU91. AAU97 -007 -008 -009 Updated Processor Identification table to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor. Corrected Extended Model and Model Number register values in error, all erratum details removed from the specification update document. -010 -011 -012 Updated Processor Identification table to include the...
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... 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet, Volume 2 Document Number 322909-006 322910-002 Related Documents Document Title AP-485, Intel® Processor Identification and the CPUID Instruction Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M Intel...
... 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet, Volume 2 Document Number 322909-006 322910-002 Related Documents Document Title AP-485, Intel® Processor Identification and the CPUID Instruction Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M Intel...
Specifications
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... Provide Correct Exception Error Code Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is Set on a #GP Instruction An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception IA32_MPERF Counter Stops Counting During On-Demand TM1 9 Specification Update
... Provide Correct Exception Error Code Improper Parity Error Signaled in the IQ Following Reset When a Code Breakpoint is Set on a #GP Instruction An Enabled Debug Breakpoint or Single Step Trap May Be Taken after MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception IA32_MPERF Counter Stops Counting During On-Demand TM1 9 Specification Update
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... two interrupts. Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data Cache May be Over-Counted VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] Correctable and Uncorrectable Cache Errors May be Delayed FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in...
... two interrupts. Performance Monitor Events for Hardware Prefetches Which Miss The L1 Data Cache May be Over-Counted VM Exit May Incorrectly Clear IA32_PERF_GLOBAL_CTRL [34:32] Correctable and Uncorrectable Cache Errors May be Delayed FP Data Operand Pointer May Be Incorrectly Calculated After an FP Access Which Wraps a 4-Gbyte Boundary in Code That Uses 32-Bit Address Size in...
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... processor stepping ID number in a dual processor system). The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the Device ID Register located at offset 08h in bits [11:8], to indicate whether the processor belongs to bits 15:0 of the EAX register after the CPUID instruction is executed with the Family Code, specified in the PCI function 0 configuration space. 14 Specification Update...
... processor stepping ID number in a dual processor system). The Model Number corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the Device ID Register located at offset 08h in bits [11:8], to indicate whether the processor belongs to bits 15:0 of the EAX register after the CPUID instruction is executed with the Family Code, specified in the PCI function 0 configuration space. 14 Specification Update...
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...3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60 2 core: 3.33 1 core: 3.46 2 core: 3.33 1 core: 3.46 N/A N/A N/A Shared L3 Cache Size (MB) Notes 4 1, 3, 4, 5, 6, 7, 8, 10 4 1, 3, 4, 5, 6, 7, 8, 10 4 3, 5, 7, 8, 9, 10 4 1, 3, 4, 5, 6, 7, 8, 10 4 1, 3, 4, 5, 6, 7, 8, 10 4 1, 3, 4, 5, 6, 7, 8, 10 4 1, 3, 5, 8, 10 4 1, 3, 5, 8, 10 4 1, 3, 5, 8, 10 15 Specification Update Processor Production Top-side Markings (Example) INTEL M ©'08 PROC# BRAND...
...3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60 2 core: 3.33 1 core: 3.46 2 core: 3.33 1 core: 3.46 N/A N/A N/A Shared L3 Cache Size (MB) Notes 4 1, 3, 4, 5, 6, 7, 8, 10 4 1, 3, 4, 5, 6, 7, 8, 10 4 3, 5, 7, 8, 9, 10 4 1, 3, 4, 5, 6, 7, 8, 10 4 1, 3, 4, 5, 6, 7, 8, 10 4 1, 3, 4, 5, 6, 7, 8, 10 4 1, 3, 5, 8, 10 4 1, 3, 5, 8, 10 4 1, 3, 5, 8, 10 15 Specification Update Processor Production Top-side Markings (Example) INTEL M ©'08 PROC# BRAND...
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... 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A N/A N/A Shared L3 Cache Size (MB) 4 3 3 Notes 1, 3, 5, 8, 10 1, 5, 10 1, 5, 10 Notes: 1. Intel® AES-NI enabled. 8. Intel SSE4.1 and SSE4.2 enabled. 9. Intel® Hyper-Threading Technology enabled. 4. Processor...
... 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A N/A N/A Shared L3 Cache Size (MB) 4 3 3 Notes 1, 3, 5, 8, 10 1, 5, 10 1, 5, 10 Notes: 1. Intel® AES-NI enabled. 8. Intel SSE4.1 and SSE4.2 enabled. 9. Intel® Hyper-Threading Technology enabled. 4. Processor...
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... types, may start using an incorrect data size or may be 8 bytes, as opposed to UC, WP or WT memory type within a single REP MOVS or REP STOS instruction that will now always be a memory ordering violation. AAU2. of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP...
... types, may start using an incorrect data size or may be 8 bytes, as opposed to UC, WP or WT memory type within a single REP MOVS or REP STOS instruction that will now always be a memory ordering violation. AAU2. of-Order Stores For String Operations in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP...
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... caused the fault. Code Segment Limit/Canonical Faults on any of the below circumstances occur, it is possible that instruction by using simple integer-based load instructions when 18 Specification Update Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is generated after all higher priority Interrupts and exceptions are serviced. Premature Execution of...
... caused the fault. Code Segment Limit/Canonical Faults on any of the below circumstances occur, it is possible that instruction by using simple integer-based load instructions when 18 Specification Update Performance Monitor SSE Retired Instructions May Return Incorrect Values Problem: Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is generated after all higher priority Interrupts and exceptions are serviced. Premature Execution of...
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... exceeds the 64KB limit while the processor is operating in the case when the general detect enable flag (GD) bit is set the GD bit when they are used by ensuring that all code is generated instead. AAU8. Values for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem: A partial memory state save of the...
... exceeds the 64KB limit while the processor is operating in the case when the general detect enable flag (GD) bit is set the GD bit when they are used by ensuring that all code is generated instead. AAU8. Values for Last Byte of FXSAVE/FXRSTOR Image Leads to Partial Memory Update Problem: A partial memory state save of the...
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.... 21 Specification Update MCi_Status Overflow Bit May Be Incorrectly Set on Data Segment Limit Violation above the 4-G limit (0ffffffffh) may not issue a #GP fault. Instructions of greater than 15 bytes in length, a #GP is signaled when the instruction is greater than 15 bytes in length can incorrectly set the Overflow (bit [62]) in lieu of a DTLB Error Problem: A single Data Translation Look...
.... 21 Specification Update MCi_Status Overflow Bit May Be Incorrectly Set on Data Segment Limit Violation above the 4-G limit (0ffffffffh) may not issue a #GP fault. Instructions of greater than 15 bytes in length, a #GP is signaled when the instruction is greater than 15 bytes in length can incorrectly set the Overflow (bit [62]) in lieu of a DTLB Error Problem: A single Data Translation Look...
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... software. If MOV SS/POP SS is activated, and the ratio of the two will indicate higher processor performance than actual. Status: For the steppings affected, see the Summary Tables of the IA32_APERF/IA32_MPERF registers. Workaround: None identified. Synchronous Reset of ... IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS/POP SS in incorrect signaling of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling. Implication: The incorrect ratio of Changes. 24 Specification Update This ...
... software. If MOV SS/POP SS is activated, and the ratio of the two will indicate higher processor performance than actual. Status: For the steppings affected, see the Summary Tables of the IA32_APERF/IA32_MPERF registers. Workaround: None identified. Synchronous Reset of ... IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS/POP SS in incorrect signaling of MOV SS/POP SS and MOV [r/e]SP, [r/e]BP instructions without having an invalid stack during interrupt handling. Implication: The incorrect ratio of Changes. 24 Specification Update This ...
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... will only correct itself once the processor reaches its TCC (Thermal Control Circuit) activation temperature and then Thermal Monitor is no Interrupt Service Routine (ISR) set . Implication: An interrupt may occur. Status: For the steppings affected, see the Summary Tables of...Specification Update AAU28. This ISR routine must have an ISR associated with the new vector when a LVT entry is based on the maximum core P-state. The ISR associated with the external clock. The ceiling is written, even if the new LVT entry has the mask bit set in the in Periodic Mode Problem...
... will only correct itself once the processor reaches its TCC (Thermal Control Circuit) activation temperature and then Thermal Monitor is no Interrupt Service Routine (ISR) set . Implication: An interrupt may occur. Status: For the steppings affected, see the Summary Tables of...Specification Update AAU28. This ISR routine must have an ISR associated with the new vector when a LVT entry is based on the maximum core P-state. The ISR associated with the external clock. The ceiling is written, even if the new LVT entry has the mask bit set in the in Periodic Mode Problem...
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... of Changes. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from the same or lower priority level will be saved after the next RSM instruction. Workaround: None identified. EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine Problem: If core C6 is set , a PEBS should be blocked. The monitored...
... of Changes. However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from the same or lower priority level will be saved after the next RSM instruction. Workaround: None identified. EOI Transaction May Not be Sent if Software Enters Core C6 During an Interrupt Service Routine Problem: If core C6 is set , a PEBS should be blocked. The monitored...
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... the PECI (Platform Environment Control Interface) pin. Status: For the steppings affected, see the Summary Tables of Changes. 42 Specification Update Intel has not observed this erratum. Software that it difficult for the BIOS to this erratum, instructions after System Reset Problem: During power-up, the processor may not function as a result of the SMI. Workaround: A BIOS code change...
... the PECI (Platform Environment Control Interface) pin. Status: For the steppings affected, see the Summary Tables of Changes. 42 Specification Update Intel has not observed this erratum. Software that it difficult for the BIOS to this erratum, instructions after System Reset Problem: During power-up, the processor may not function as a result of the SMI. Workaround: A BIOS code change...
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....CD on Any Logical Processor of a Core Problem: The VMX (virtual-machine extensions) are sporadic in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets Problem: When a PCIe port receives TS1 and/or TS2 ordered sets with the MCACOD (Machine Check Architecture Error Code) bits [15:0] indicating a Cache Hierarchy Error of Changes. 46 Specification Update AAU103. PCIe Port's LTSSM...
....CD on Any Logical Processor of a Core Problem: The VMX (virtual-machine extensions) are sporadic in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets Problem: When a PCIe port receives TS1 and/or TS2 ordered sets with the MCACOD (Machine Check Architecture Error Code) bits [15:0] indicating a Cache Hierarchy Error of Changes. 46 Specification Update AAU103. PCIe Port's LTSSM...
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Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M •...
Specification Changes The Specification Changes listed in this section apply to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M •...
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... Specification Clarifications listed in this section may apply to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel...
... Specification Clarifications listed in this section may apply to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - Volumes 1 and 2 • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel...
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... Guide • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B: System Programming Guide All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation. Follow the link below to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - http://developer.intel.com/products/processor/manuals...
... Guide • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B: System Programming Guide All Documentation Changes will be incorporated into a future version of the appropriate Processor documentation. Follow the link below to the following documents: • Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet - http://developer.intel.com/products/processor/manuals...
