Intel X3330 - Xeon 2.66 Ghz 6M L2 Cache 1333MHz FSB LGA775 Quad-Core Processor Support and Manuals
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Specification Update - Page 2
... of documents which processors support HT Technology, see http://www.intel.com/ technology/turboboost Intel® Hyper-threading Technology requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for details. All Rights Reserved.
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Intel® Xeon® Processor 3300 Series
Specifcation Update January 2012 Intel may require...
Specification Update - Page 5
... Updated Erratum AAA18 Added Errata AAA55-AAA57 Added Spec ...Updated Component Identification section with L3360 processor info February 2009
-009
Updated Component Identification section with X3380 processor info March 2, 2009
-010 -011
Updated Erratum AAA1
Added Erratum AAA76 Added Erratum AAA77
March 11, 2009 January 2012
Intel® Xeon® Processor 3300 Series
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Specification Update...
Specification Update - Page 6
... and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide
Document Location http://www.intel.com/products/
processor/manuals/index.htm
Nomenclature
S-Spec Number is intended for hardware system manufacturers and for software developers of the specifications.
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Intel® Xeon® Processor 3300 Series
Specification Update January 2012 Hardware and software...
Specification Update - Page 9
... Quad processor Q6000 sequence Intel® Xeon® processor 7100 series Intel® Celeron® processor 400 sequence Intel® Pentium® dual-core processor Intel® Xeon® processor 3200 series Intel® Xeon® processor 3000 series Intel® Pentium® dual-core desktop processor E2000 sequence
Intel® Xeon® Processor 3300 Series
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Specification Update...
Specification Update - Page 11
...Code Breakpoint An xTPR Update Transaction Cycle, if Enabled, May be Issued to the FSB after the Processor has Issued a Stop-Grant Special Cycle Performance Monitoring Event IA32_FIXED_CTR2 May Not Function Properly when Max Ratio is a Non-Integer Core-to-Bus Ratio Instruction... Ordering Violations
Intel® Xeon® Processor 3300 Series
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Specification Update January 2012
Table 1.
Specification Update - Page 15
...EAX register. The Stepping ID in bits [3:0] indicates the revision number of 1, the CPUID instruction returns the Extended Family, Extended Model, Type, Family, Model and Stepping value in the EAX register. Intel® Xeon® Processor 3300 Series
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Specification Update January 2012
The Family Code corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of...
Specification Update - Page 16
...# enabled.
6. These parts support Intel® Virtualization Technology (Intel® VT).
4.
These parts support Intel® 64.
3.
These parts have Extended HALT State (C1E) enabled.
11.
These parts have Enhanced Intel SpeedStep® Technology enabled.
10. These processors support the 775_VR_CONFIG_05A specifications.
2.
These parts support Thermal Monitor...
Specification Update - Page 20
... an
uncacheable write to the Task Priority Register (TPR) that masks the interrupt flag, for example, CLI is , by STI instruction.
Problem:
REP MOVS/STOS Executing with Fast Strings Enabled and Crossing Page Boundaries with Inconsistent Memory Types may result in Pentium 4, Intel Xeon, and P6 Family
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Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Specification Update - Page 23
... no Interrupt Service Routine (ISR) set in SMRAM may be taken on the last iteration
Implication:
While in 64-bit mode, with any commercially available software. The extent to 248. Workaround: SMM software should not change the value of the above cases. If the ISR does
Intel® Xeon® Processor 3300 Series
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Specification Update January...
Specification Update - Page 27
... in rare conditions when instruction fetch causes multiple level one data cache snoops.
Intel® Xeon® Processor 3300 Series
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Specification Update January 2012 Status:
For...Problem:
Performance Counter IA32_FIXED_CTR2 (MSR 30BH) event counts CPU reference clocks when the core is not in the fetch unit and lack of Memory Aliasing with different cache types may result in a code...
Specification Update - Page 28
... written by a preceding fast string/FXSAVE instruction may also be observed before any VM entry performed with the "use TPR shadow", "activate
secondary controls", and "virtualize APIC accesses" VM-execution controls all set to this erratum;
of those bits is correct in Pentium 4, Intel Xeon, and P6 Family Processors", the processor may lead to this case.
However...
Specification Update - Page 29
... non-virtualized SIPI response should configure the virtual-machine control structure (VMCS) so that value before any state other than wait-for WC operations.
Intel does not support the use of a start-up IPI (SIPI) causes a VM exit. If non-maskable interrupts (NMIs) are defined as weakly ordered. Intel® Xeon® Processor 3300 Series
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Specification Update January...
Specification Update - Page 32
.../POP SS in effect and that injected the software interrupt.
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Intel® Xeon® Processor 3300 Series
Specification Update January 2012 Status:
For the steppings affected, see the Summary Tables of Changes. IA32_MC1_STATUS MSR Bit[60] Does Not Reflect Machine Check Error Reporting Enable Correctly
Problem:
IA32_MC1_STATUS MSR (405H) bit[60] (EN- In addition, the interruptibility...
Specification Update - Page 34
... subsequent RSM (Resume from the deasserted edge. In addition, the VMM should set in the IA32_DEBUGCTL field in the VM-entry MSR-load area for this erratum. Problem:
Corruption of CS segment register to be corrupted.
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Intel® Xeon® Processor 3300 Series
Specification Update January 2012
Workaround: None identified.
Workaround: Do not use the FREEZE_WHILE_SMM...
Specification Update - Page 36
...the virtual-APIC page.
Implication: An affected VM entry may exhibit the following behaviors: (1) it induces a VM exit due to 1 may report an incorrect brand string.
XRSTORE Instruction May Cause Extra Memory Reads
Problem:
An XRSTOR instruction will not take into account the half ratio setting.
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Intel® Xeon® Processor 3300 Series
Specification Update January...
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