Intel P9500 - Core 2 Duo 2.53 GHz 6M L2 Cache 1066MHz FSB Socket P Mobile Processor Support and Manuals
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Popular Intel P9500 Manual Pages
Data Sheet - Page 2
... or errors known as the property of the I2C bus/protocol or the SMBus bus/protocol may be obtained by calling1-800-548-4725, or by visiting Intel's website at any features or instructions marked "reserved" or "undefined." Copyright © 2002-2007, Intel Corporation
*Other names and brands may require licenses from published specifications.
Contact...
Data Sheet - Page 4
6.4 Processor Information ROM and Scratch EEPROM Supported SMBus Transactions ...85
6.5 Thermal Sensing Device 86 6.6 Thermal Sensing Device Supported SMBus Transactions 87 6.7 Thermal Sensing Device Registers 88
6.7.1 Thermal ... INT (I 100 A.1.42 IP[1:0]# (I 100 A.1.43 LEN[2:0]# (I/O 100 A.1.44 LINT[1:0] (I 100
4
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet
Data Sheet - Page 9
...Register stack engine for multiprocessor scalability:
- Support for data-intensive applications.
- Full SMBus compatibility. - Built-in superior Instruction-Level Parallelism (ILP). Built-in programmable EEPROM. - This feature is applicable to four physical processors on one processor. Reduces virtualization complexity. - Minimize L3 cache errors.
High-bandwidth system bus for...
Data Sheet - Page 10
...Hat, Red Flag, and other distributions; And with industry support growing and future Intel Itanium processor family advances already in development, your Itanium-based server investment...Intel® Itanium® Processor 9000 and 9100 Series Datasheet HP NonStop*; The Dual-Core Intel® Itanium® processor 9000 and 9100 series delivers new levels of flexibility, reliability, performance...
Data Sheet - Page 11
...thermal specifications for the DualCore Intel Itanium processor 9000 and 9100 series for a wide range of each instruction.
This provides a combination of abundant resources to system firmware and operating systems across a large scheduling scope, thereby exposing available Instruction Level Parallelism (ILP) to large SMP servers.
PAL firmware supports processor initialization, error...
Data Sheet - Page 12
... SAL is not supported and has not been validated by Intel. Mixing components of... this document is inverted. In the case of lines where the name does not imply an active state but describes part...Intel® Itanium® Processor 9000 and 9100 Series Datasheet
1.3 1.4 1.5
Introduction
The System Abstraction Layer (SAL) firmware contains platform-specific firmware...
Data Sheet - Page 13
...; Itanium® Architecture Software Developer's Manual, Volume 3: Instruction Set Reference Intel® Itanium® 2 Processor Reference Manual for Software Development and Optimization Intel® Itanium® Processor Family System Abstraction Layer Specification ITP700 Debug Port Design Guide System Management Bus Specification
Contact your Intel representative or check http://developer...
Data Sheet - Page 16
..." refers to VCTERM.
The processor system bus supports both ends of the bus. Please see the TERMA and TERMB pin description in Table 2-8 and Table 2-9, respectively.
16
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet See the Intel® Itanium®
2 Processor Hardware Developer's Manual for these signals. The processor system bus requires termination...
Data Sheet - Page 75
... Specifications
This chapter provides a description of the processor system management feature. Figure 5-1. Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Thermal Features
Thermal Alert
ETM
Thermal Trip
5.1.1
Time
000653b
Thermal Alert
THRMALERT# is a programmable thermal alert signal which is part of the thermal features relating to the Dual-Core Intel Itanium...
Data Sheet - Page 81
...processor select in systems which do not support the SMBus, or only support a partial implementation.
Thermal Sensing Device SMBus Addressing on the Dual-Core Intel® Itanium® Processor 9000 and 9100 series
Address (Hex) Upper Address1
Processor Select
8-Bit Address Word on the processor...set the Hi-Z state for the serial bus transaction. A tri-state or "Z" state on the processor ...
Data Sheet - Page 85
...Intel® Itanium™ Architecture Software Developer's Manual for other data at the system vendor's discretion (Intel will result in this signal.
6.4
Processor Information ROM and Scratch EEPROM Supported SMBus Transactions
The processor... the SMBus start bit, 'P' represents a stop . System Management Feature Specifications
Notes:
1. The page write operates the same way as there are ...
Data Sheet - Page 92
... that is less than 64 GB (that support the 64 GByte (36-bit) address space must set ASZ[1:0]# to the transaction when ASZ[1:0]# equals...support larger than 64 GB (that is equal to or greater than the 64 GByte (36-bit) address space must set...processor derives its internal clock by multiplying the BCLKp and BCLKn frequency by the request initiator during the second clock of the processor...
Data Sheet - Page 94
...
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series Datasheet The L2 and L3 caches are system support signals used for ownership of its requests are the physical bus request pins that prevents reliable future operation. BINIT# is a wired-OR signal.
If BINIT# observation is disabled during power-on specific clock edges...
Data Sheet - Page 101
...the setup and hold times.
If NMI is asserted during power-on the Ab[5]# pin. Recognition of detail that involve data transfer. This allows a memory controller to ignore memory updates due...platform specific firmware. Signals Reference
A.1.46
A.1.47 A.1.48 A.1.49 A.1.50
NMI (I )
The Power Good (PWRGOOD) signal must be asserted (H) after the EOI is executed by the NMI service routine...
Data Sheet - Page 104
... tools.
Once THRMTRIP# is set well above the normal operating ...processor. This signal can be lost if the processor goes into the processor. A.1.65
TMS (I /O)
The TLB Purge Not Done (TND#) signal is an IEEE 1149.1 compliant TAP specification support signal used by the assertion of a TLB Purge instruction...bus.
104
Dual-Core Intel® Itanium® Processor 9000 and 9100 Series...
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