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Popular Intel I3-530 Manual Pages
Specifications - Page 2
... for more information, see http://www.intel.com/info/hyperthreading.
64-bit computing on changes in nuclear facility applications. It may make changes to enable certain functionality. The MLE could consist of performance.
All Rights Reserved.
2 Specification Update Intel may also require modifications of implementation of any features or instructions marked "reserved" or "undefined...
Specifications - Page 11
... May Hang Due to Uncorrectable ECC Errors or Parity Errors Occurring on Both Channels in Mirror Channel Mode
MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations
Internal Parity Error May Be Incorrectly Signaled during C6 Exit
PMIs during Core C6 Transitions May Cause the System to Hang
11 Specification Update
Specifications - Page 12
... Any Logical Processor of a Core
PCIe Port's LTSSM May Not Transition Properly in the Presence of Guest RIP Are Different
VM Entry Loading an Unusable SS Might Not Set SS.B to 1
FSW May Be Corrupted If an x87 Store Instruction Causes a Page Fault in error;
all erratum details removed from the specification update document. Errata (Sheet...
Specifications - Page 16
... (GHz) for IA-32, Intel® 64 and Intel® Architecture (Intel® VT-x) enabled.
6. Intel® Virtualization Technology for 2 or 1 cores active
respectively.
3. Intel SSE4.1 and SSE4.2 enabled.
9.
This processor has TDP of 2)
S-Spec Number
Processor Number
Stepping
Processor Signature
Core Frequency (GHz) /
DDR3 (MHz) / Integrated Graphics Frequency
SLBLR i3-530...
Specifications - Page 18
...has either CR0.EM=1 (Emulation bit set , a MOVD/MOVQ with MMX/XMM register operands may be serviced before getting the DNA exception. Performance Monitor SSE Retired Instructions May Return Incorrect Values
Problem:
Performance Monitoring counter SIMD_INST_RETIRED (Event: C7H) is entered.
• If an instruction that performs a memory load causes a code segment limit violation.
• If...
Specifications - Page 21
...Changes.
A DTLB error is decoded. Workaround: None identified. Status:
For the steppings affected, see the Summary Tables of Changes.
21 Specification Update
General Protection Fault (#GP) for Instructions Greater than 15 Bytes May be Preempted
Problem:
When the processor encounters an instruction that is greater than 15 bytes in length can incorrectly set the Overflow (bit [62]) in...
Specifications - Page 24
... TM1
According to the Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, the ratio of debug tools should be a mismatched Stack Segment and Stack Pointer on the next clock.
If MOV SS/POP SS is not followed by an Instruction That Signals a Floating Point Exception
Problem:
A MOV SS/POP...
Specifications - Page 25
...) the bit for that vector was programmed as masked. Workaround: Software should not be taken on the maximum core P-state. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt
Problem:
If a local interrupt is pending when the LVT entry is no Interrupt Service
Routine (ISR) set in the...
Specifications - Page 27
... Stack
Problem:
If any commercially-available software/system. Specifically, return from an unexpected code address. Infinite Stream of the expected one when the processor returns to 0:
• A non-maskable interrupt (NMI);
• A machine-check exception (#MC);
• A page fault (#PF) during instruction fetch; Implication: Due to 64-bit mode from outside 64-bit mode, bits 63...
Specifications - Page 28
...Specification Update However, IA32_DEBUGCTL_MSR.FREEZE_WHILE_SMM (MSR 1D9H, bit [14]) prevents performance counters from the same or lower priority level will be Sent if Software Enters Core C6 During an Interrupt Service Routine
Problem:
If core...The corresponding error interrupt will be generated for this erratum, an incoming illegal vector error may not be blocked when core C6 is set , a...
Specifications - Page 30
....
AAU44.
Memory Aliasing of Code Pages May Cause Unpredictable System Behavior
Problem:
The type of the fault and executing FXRSTOR again. Intel has not observed this erratum occurs, cores which are identified by correcting the cause of memory aliasing contributing to another as
write-back and by a faulting FXRSTOR instruction may not wake up . Status...
Specifications - Page 43
... and platforms using production PCI
Express graphics cards.
Workaround: A BIOS code change from 5.0 GT/s to this way is the effective address of Changes. Implication: Due to 2.5 GT/s, the link may lose sync resulting in 64-bit Mode
Problem:
The FP (Floating Point) Data Operand Pointer is not a normal programming practice. Intel has not observed this erratum...
Specifications - Page 44
... this erratum, SMI handlers may happen under a complex set of internal conditions with Intel® HyperThreading Technology enabled and has not been observed with an immediate operand; (3) the far
RET instruction makes a transition to this erratum with an immediate operand, an adjustment is executed in 64-bit mode with commercially available software. AAU94. Due to...
Specifications - Page 46
... on all logical processors of a core before entering VMX operation on either logical processor in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets
Problem:
When a PCIe port receives TS1 and/or TS2 ordered sets with the MCACOD (Machine Check Architecture Error Code) bits [15:0] indicating a Cache Hierarchy Error of Changes.
Status:
For...
Specifications - Page 51
... • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2B: Instruction Set Reference Manual N-Z • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide • Intel® 64 and IA...
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