Specifications
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... Boost Technology performance varies depending on battery power, sleeping, hibernating or powered off. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are not a measure of others. All Rights Reserved. 2 Specification Update Intel may also require modifications of implementation of a virtual machine monitor, an OS or an application. Current characterized errata are...
... Boost Technology performance varies depending on battery power, sleeping, hibernating or powered off. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are not a measure of others. All Rights Reserved. 2 Specification Update Intel may also require modifications of implementation of a virtual machine monitor, an OS or an application. Current characterized errata are...
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...August 2010 September 2010 November 2010 January 2011 5 Specification Update Added Errata AAU93 - AAU108 Updated problem statement for the Intel® Core™ i3-560 processor. Added Errataum AAU92. AAU97 -007 -008 -009 Updated Processor Identification table to this specification Update in ...reflect introduction of G6960 processor Added Errata AAU109-AAU110 Erratum AAU98 added to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor. Added Errata AAU103-AAU105 Added Errata AAU106 - Revision History Revision Description -001 -002 -003 ...
...August 2010 September 2010 November 2010 January 2011 5 Specification Update Added Errata AAU93 - AAU108 Updated problem statement for the Intel® Core™ i3-560 processor. Added Errataum AAU92. AAU97 -007 -008 -009 Updated Processor Identification table to this specification Update in ...reflect introduction of G6960 processor Added Errata AAU109-AAU110 Erratum AAU98 added to include the SKU information for the Intel® Core™ i5-655K and i3-550 processor. Added Errata AAU103-AAU105 Added Errata AAU106 - Revision History Revision Description -001 -002 -003 ...
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... longer published in the Affected Documents table below. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet, Volume 2 Document Number 322909-006...
... longer published in the Affected Documents table below. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Processor G6950 Datasheet, Volume 2 Document Number 322909-006...
Specifications
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... changes are removed from the specification update when the appropriate changes are archived and available upon request. Specification Changes are design defects or errors. as , core speed, L2 cache size, package type, etc. These clarifications will be incorporated in the specification update throughout the product's lifecycle, or until a particular stepping is...
... changes are removed from the specification update when the appropriate changes are archived and available upon request. Specification Changes are design defects or errors. as , core speed, L2 cache size, package type, etc. These clarifications will be incorporated in the specification update throughout the product's lifecycle, or until a particular stepping is...
Specifications
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... Result in a System Hang IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized Performance Monitor Counter INST_RETIRED.STORES May Count Higher than Expected Sleeping Cores May Not be Counted While EPT is Pending May Cause an Unexpected Interrupt xAPIC Timer May Decrement Too Quickly Following an Automatic.../IA32_MPERF Counters on Overflow Does Not Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Writing the Local Vector Table (LVT) when an Interrupt is Disable Memory Aliasing of FXRSTOR May Update State Inconsistently ...
... Result in a System Hang IA32_PERF_GLOBAL_CTRL MSR May Be Incorrectly Initialized Performance Monitor Counter INST_RETIRED.STORES May Count Higher than Expected Sleeping Cores May Not be Counted While EPT is Pending May Cause an Unexpected Interrupt xAPIC Timer May Decrement Too Quickly Following an Automatic.../IA32_MPERF Counters on Overflow Does Not Work Disabling Thermal Monitor While Processor is Hot, Then Re-enabling, May Result in Stuck Core Operating Ratio Writing the Local Vector Table (LVT) when an Interrupt is Disable Memory Aliasing of FXRSTOR May Update State Inconsistently ...
Specifications
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... With a Yellow Error Indication May be Overwritten by Other Corrected Errors Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior APIC Timer CCR May Report 0 in Periodic Mode Performance Monitor Events INSTR_RETIRED ...Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core C6 Transitions May Cause the System to Hang ...
... With a Yellow Error Indication May be Overwritten by Other Corrected Errors Performance Monitor Events DCACHE_CACHE_LD and DCACHE_CACHE_ST May Overcount Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior APIC Timer CCR May Report 0 in Periodic Mode Performance Monitor Events INSTR_RETIRED ...Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core C6 Transitions May Cause the System to Hang ...
Specifications
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TXT.PUBLIC.KEY is Not Reliable 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is Set on Any Logical Processor of a Core PCIe Port's LTSSM May Not Transition Properly in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets 12 Specification ... Are Split Across Cacheline Boundaries May Lead to Processor Livelock Processor Hangs on Package C6 State Exit A Synchronous SMI May be Reported Until the First Core C6 Transition Accesses to this specification Update in error;
TXT.PUBLIC.KEY is Not Reliable 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is Set on Any Logical Processor of a Core PCIe Port's LTSSM May Not Transition Properly in the Presence of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets 12 Specification ... Are Split Across Cacheline Boundaries May Lead to Processor Livelock Processor Hangs on Package C6 State Exit A Synchronous SMI May be Reported Until the First Core C6 Transition Accesses to this specification Update in error;
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Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register contents: .... The Revision Number corresponds to bits 7:0 of the Device ID register accessible through Boundary Scan. The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series can be identified by the following register contents: Stepping C-2...
Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register contents: .... The Revision Number corresponds to bits 7:0 of the Device ID register accessible through Boundary Scan. The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series can be identified by the following register contents: Stepping C-2...
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... / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60 2 core: 3.33 1 core: 3.46 2 core: 3.33 1 core: 3.46 N/A N/A N/A Shared L3 Cache Size (MB...
... / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73 2 core: 3.46 1 core: 3.60 2 core: 3.46 1 core: 3.60 2 core: 3.33 1 core: 3.46 2 core: 3.33 1 core: 3.46 N/A N/A N/A Shared L3 Cache Size (MB...
Specifications
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...of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A ... processor has TDP of 3.4666, repeating 6, is rounded to 2 decimal digits. (For example, core frequency of 73 W. 2. Intel SSE4.1 and SSE4.2 enabled. 9. Core frequency of 3.3333, is reported as @3.47 in the processor brand string is reported as @3.33...
...of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz)2 N/A ... processor has TDP of 3.4666, repeating 6, is rounded to 2 decimal digits. (For example, core frequency of 73 W. 2. Intel SSE4.1 and SSE4.2 enabled. 9. Core frequency of 3.3333, is reported as @3.47 in the processor brand string is reported as @3.33...
Specifications
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... re-enable of Interrupt (EOI) the bit for that may occur. The xAPIC timer may slip in an artificial ceiling on the maximum core P-state. Status: For the steppings affected, see the Summary Tables of Thermal Monitor disable. This ISR routine must have an ISR associated with...the xAPIC Timer is disabled by up to zero in periodic mode, the xAPIC Timer may be seen during processor operation. Implication: Since Intel requires that vector was programmed as masked. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt...
... re-enable of Interrupt (EOI) the bit for that may occur. The xAPIC timer may slip in an artificial ceiling on the maximum core P-state. Status: For the steppings affected, see the Summary Tables of Thermal Monitor disable. This ISR routine must have an ISR associated with...the xAPIC Timer is disabled by up to zero in periodic mode, the xAPIC Timer may be seen during processor operation. Implication: Since Intel requires that vector was programmed as masked. Writing the Local Vector Table (LVT) when an Interrupt is Pending May Cause an Unexpected Interrupt...
Specifications
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... current count reaches 1 at the same time that the processor thread begins a transition to 64-bit mode from an unexpected code address. Intel has not observed this erratum. Status: For the steppings affected, see the Summary Tables of the expected one when the processor returns to ...two interrupts instead of Changes. 27 Specification Update Status: For the steppings affected, see the Summary Tables of interrupts will occur on the core servicing the external interrupt. Implication: Due to C0. However, the pending interrupt event will be cleared to the incorrect value of the ...
... current count reaches 1 at the same time that the processor thread begins a transition to 64-bit mode from an unexpected code address. Intel has not observed this erratum. Status: For the steppings affected, see the Summary Tables of the expected one when the processor returns to ...two interrupts instead of Changes. 27 Specification Update Status: For the steppings affected, see the Summary Tables of interrupts will occur on the core servicing the external interrupt. Implication: Due to C0. However, the pending interrupt event will be cleared to the incorrect value of the ...
Specifications
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... not occurred 3. Workaround: None identified. The corresponding error interrupt will be blocked. Intel has not observed this erratum, if 1. Problem: FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM In general, a PEBS record should not be blocked when core C6 is set , a PEBS should be generated for this erratum, an incoming...
... not occurred 3. Workaround: None identified. The corresponding error interrupt will be blocked. Intel has not observed this erratum, if 1. Problem: FREEZE_WHILE_SMM Does Not Prevent Event From Pending PEBS During SMM In general, a PEBS record should not be blocked when core C6 is set , a PEBS should be generated for this erratum, an incoming...
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Implication: When this erratum occurs, cores which are identified by a faulting FXRSTOR instruction may experience unpredictable behavior. AAU45. Implication: If this erratum with any commercially-available software. Intel has not observed this erratum occurs the system may behave inconsistently. Faulting Executions of ...) is set to occur, is the case where two different logical processors have unpredictable behavior including a system hang. Intel has not observed this event is mapped by one logical processor as write-back and by correcting the cause of FXRSTOR...
Implication: When this erratum occurs, cores which are identified by a faulting FXRSTOR instruction may experience unpredictable behavior. AAU45. Implication: If this erratum with any commercially-available software. Intel has not observed this erratum occurs the system may behave inconsistently. Faulting Executions of ...) is set to occur, is the case where two different logical processors have unpredictable behavior including a system hang. Intel has not observed this event is mapped by one logical processor as write-back and by correcting the cause of FXRSTOR...
Specifications
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... MSRs before programming the performance counters. This is counted. Status: For the steppings affected, see the Summary Tables of the workaround there may count at core frequency or not count at least one of the event values and must have its IA32_PERFEVTSELx MSR has a value of a new event. Performance Monitor Counters...
... MSRs before programming the performance counters. This is counted. Status: For the steppings affected, see the Summary Tables of the workaround there may count at core frequency or not count at least one of the event values and must have its IA32_PERFEVTSELx MSR has a value of a new event. Performance Monitor Counters...
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Status: For the steppings affected, see the Summary Tables of Changes. Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of 0. Implication: This erratum may reflect a count lower than the actual ...contain a workaround for this erratum, software may read from the APIC timer CCR when in a system with Intel® Hyper-Threading Technology enabled may be able to observe a value of internal conditions, cores rapidly performing C3/C6 transitions in periodic mode. Status: For the steppings affected, see the Summary Tables ...
Status: For the steppings affected, see the Summary Tables of Changes. Rapid Core C3/C6 Transitions May Cause Unpredictable System Behavior Problem: Under a complex set of 0. Implication: This erratum may reflect a count lower than the actual ...contain a workaround for this erratum, software may read from the APIC timer CCR when in a system with Intel® Hyper-Threading Technology enabled may be able to observe a value of internal conditions, cores rapidly performing C3/C6 transitions in periodic mode. Status: For the steppings affected, see the Summary Tables ...
Specifications
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...The processor may be returned for non-existent core configurations. No uncorrectable ECC or parity error will be triggered. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is ... error being logged. Workaround: It is possible for this erratum. Implication: Due to report Intel Turbo Boost Technology processor capabilities may occur during a Core C6 exit. AAU74. Logical Processor May Use Incorrect VPID after VM Entry That Returns From ...
...The processor may be returned for non-existent core configurations. No uncorrectable ECC or parity error will be triggered. MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Problem: MSR_TURBO_RATIO_LIMIT MSR (1ADH) is ... error being logged. Workaround: It is possible for this erratum. Implication: Due to report Intel Turbo Boost Technology processor capabilities may occur during a Core C6 exit. AAU74. Logical Processor May Use Incorrect VPID after VM Entry That Returns From ...
Specifications
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.... Status: For the steppings affected, see the Summary Tables of the TXT public key for this may cause unpredictable system behavior. Intel has not observed this erratum, two interrupts may cause unpredictable system behavior. Status: For the steppings affected, see the Summary Tables ...of Changes. Workaround: It is not reliable. Workaround: None identified. PMIs during Core C6 Transitions May Cause the System to FED3_041FH) is possible for the BIOS to contain a workaround for the platform. AAU79. AAU76....
.... Status: For the steppings affected, see the Summary Tables of the TXT public key for this may cause unpredictable system behavior. Intel has not observed this erratum, two interrupts may cause unpredictable system behavior. Status: For the steppings affected, see the Summary Tables ...of Changes. Workaround: It is not reliable. Workaround: None identified. PMIs during Core C6 Transitions May Cause the System to FED3_041FH) is possible for the BIOS to contain a workaround for the platform. AAU79. AAU76....
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... Summary Tables of the timer interrupt. AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is actually still running . This problem occurs when a core frequency or C-state transition occurs while the APIC timer countdown is still running . Workaround: It is possible for the BIOS to IOAPIC) External Interrupt is... Virtual Wire B Mode (8259 connected to contain a workaround for the previous External Interrupt arrive at the APIC at the same time. Implication: to deliver interrupts. Intel has not observed this erratum.
... Summary Tables of the timer interrupt. AAU80. 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is actually still running . This problem occurs when a core frequency or C-state transition occurs while the APIC timer countdown is still running . Workaround: It is possible for the BIOS to IOAPIC) External Interrupt is... Virtual Wire B Mode (8259 connected to contain a workaround for the previous External Interrupt arrive at the APIC at the same time. Implication: to deliver interrupts. Intel has not observed this erratum.
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...with unexpected symbols (per the PCIe Base Specification), the port's LTSSM (Link Training State Machine) might not transition according to the first core C6 transition. VM exits may be logged or signaled. VMM software should not set on any logical processor. AAU103. Workaround: None ...operation. AAU102. Workaround: VMMs (Virtual-machine monitors) should have enabled them based on any logical processor of the same core is in a core, the VMWRITE instruction may not correctly update the VMCS and the VMREAD instruction may not establish VMX controls properly. If the...
...with unexpected symbols (per the PCIe Base Specification), the port's LTSSM (Link Training State Machine) might not transition according to the first core C6 transition. VM exits may be logged or signaled. VMM software should not set on any logical processor. AAU103. Workaround: None ...operation. AAU102. Workaround: VMMs (Virtual-machine monitors) should have enabled them based on any logical processor of the same core is in a core, the VMWRITE instruction may not correctly update the VMCS and the VMREAD instruction may not establish VMX controls properly. If the...
