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... Boost Technology requires a PC with a processor with Intel® Virtualization Technology (Intel® Virtualization Technology (Intel® VT-x) and Intel® Virtualization Technology for conflicts or incompatibilities arising from published specifications. Consult with your system delivers Intel Turbo Boost Technology. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of performance...
... Boost Technology requires a PC with a processor with Intel® Virtualization Technology (Intel® Virtualization Technology (Intel® VT-x) and Intel® Virtualization Technology for conflicts or incompatibilities arising from published specifications. Consult with your system delivers Intel Turbo Boost Technology. Intel, Intel Core, Celeron, Pentium, Intel Xeon, Intel Atom, Intel SpeedStep, and the Intel logo are trademarks or registered trademarks of performance...
Specifications
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Contents Contents Revision History ...5 Preface ...6 Summary Tables of Changes 8 Identification Information 14 Errata ...17 Specification Changes 49 Specification Clarifications 50 Documentation Changes 51 § 3 Specification Update
Contents Contents Revision History ...5 Preface ...6 Summary Tables of Changes 8 Identification Information 14 Errata ...17 Specification Changes 49 Specification Clarifications 50 Documentation Changes 51 § 3 Specification Update
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... error, all erratum details removed from the specification update document. -010 -011 -012 Updated Processor Identification table to this specification Update in Component Identification table. Added Documentation Changes AAU1-AAU3. Added Errata AAU93 - AAU108 Updated problem statement for the Intel® Core™ i5-655K and i3-550 processor. Corrected Extended Model and Model...
... error, all erratum details removed from the specification update document. -010 -011 -012 Updated Processor Identification table to this specification Update in Component Identification table. Added Documentation Changes AAU1-AAU3. Added Errata AAU93 - AAU108 Updated problem statement for the Intel® Core™ i5-655K and i3-550 processor. Corrected Extended Model and Model...
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... Nomenclature are consolidated into the specification update and are no longer published in the Affected Documents table below. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and...
... Nomenclature are consolidated into the specification update and are no longer published in the Affected Documents table below. Affected Documents Document Title Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series Datasheet, Volume 1 Intel® Core™ i5-600, i3-500 Desktop Processor Series and...
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... stepping are archived and available upon request. These clarifications will be incorporated in the processor identification information table. Under these circumstances, errata removed from the specification update when the appropriate changes are design defects or errors. Products are modifications to a complex design situation. as , core speed, L2 cache size, package type...
... stepping are archived and available upon request. These clarifications will be incorporated in the processor identification information table. Under these circumstances, errata removed from the specification update when the appropriate changes are design defects or errors. Products are modifications to a complex design situation. as , core speed, L2 cache size, package type...
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... may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. There are no plans to this stepping. Summary Tables of Changes The following notations: Codes Used in Summary Tables ... erratum. Status Doc: Plan Fix: Fixed: No Fix: Document change does not apply to left of the product. Specification Change or Clarification that applies to fix this document. Intel may be implemented. Row Change bar to listed stepping. This erratum has been previously fixed.
... may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. There are no plans to this stepping. Summary Tables of Changes The following notations: Codes Used in Summary Tables ... erratum. Status Doc: Plan Fix: Fixed: No Fix: Document change does not apply to left of the product. Specification Change or Clarification that applies to fix this document. Intel may be implemented. Row Change bar to listed stepping. This erratum has been previously fixed.
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... MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception IA32_MPERF Counter Stops Counting During On-Demand TM1 9 Specification Update
... MOV SS/ POP SS Instruction if it is Followed by an Instruction That Signals a Floating Point Exception IA32_MPERF Counter Stops Counting During On-Demand TM1 9 Specification Update
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all erratum details removed from the specification update document. Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP onto the Stack Infinite Stream of Interrupts May Occur if an ... Not Count NT Stores to Local DRAM Correctly EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change Back to this specification Update in Periodic Mode Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Changing the Memory Type for an...
all erratum details removed from the specification update document. Delivery of Certain Events Immediately Following a VM Exit May Push a Corrupted RIP onto the Stack Infinite Stream of Interrupts May Occur if an ... Not Count NT Stores to Local DRAM Correctly EFLAGS Discrepancy on Page Faults and on EPT-Induced VM Exits after a Translation Change Back to this specification Update in Periodic Mode Reported Memory Type May Not Be Used to Access the VMCS and Referenced Data Structures Changing the Memory Type for an...
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... The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity Errors Occurring on Both Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core...
... The Memory Controller May Hang Due to Uncorrectable ECC Errors or Parity Errors Occurring on Both Channels in Mirror Channel Mode MSR_TURBO_RATIO_LIMIT MSR May Return Intel® Turbo Boost Technology Core Ratio Multipliers for Non-Existent Core Configurations Internal Parity Error May Be Incorrectly Signaled during C6 Exit PMIs during Core...
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...Properly in the Presence of a Page-Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to this specification Update in error; TXT.PUBLIC.KEY is Not Reliable 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is possible ... PECI Bus May Be Tri-stated after System Reset The Combination of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets 12 Specification Update Errata (Sheet 4 of 5) Number Steppings C-2 K-0 Status AAU77 X X No Fix AAU78 X X No Fix AAU79 X AAU80 X Fixed Fixed AAU82 X X No Fix AAU83 X ...
...Properly in the Presence of a Page-Split Lock Access And Data Accesses That Are Split Across Cacheline Boundaries May Lead to this specification Update in error; TXT.PUBLIC.KEY is Not Reliable 8259 Virtual Wire B Mode Interrupt May Be Dropped When it is possible ... PECI Bus May Be Tri-stated after System Reset The Combination of TS1 or TS2 Ordered Sets That Have Unexpected Symbols Within those Sets 12 Specification Update Errata (Sheet 4 of 5) Number Steppings C-2 K-0 Status AAU77 X X No Fix AAU78 X X No Fix AAU79 X AAU80 X Fixed Fixed AAU82 X X No Fix AAU83 X ...
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... the VMCS Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior Execution of VMPTRLD May Corrupt Memory If Current-VMCS Pointer is Invalid PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Specification Changes Number SPECIFICATION CHANGES None for this revision of this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS None...
... the VMCS Intel Turbo Boost Technology Ratio Changes May Cause Unpredictable System Behavior Execution of VMPTRLD May Corrupt Memory If Current-VMCS Pointer is Invalid PerfMon Overflow Status Can Not be Cleared After Certain Conditions Have Occurred Specification Changes Number SPECIFICATION CHANGES None for this revision of this specification update. Specification Clarifications Number SPECIFICATION CLARIFICATIONS None...
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...in the PCI function 0 configuration space. 3. Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register ...[11:8], to indicate whether the processor belongs to the processor signature output value in the PCI function 0 configuration space. 14 Specification Update The Extended Model, bits [19:16] in conjunction with the Family Code, specified in the PCI function 0 configuration ...
...in the PCI function 0 configuration space. 3. Identification Information Component Identification using Programming Interface The Intel® Core™ i5-600, i3-500 Desktop Processor Series and Intel® Pentium® Desktop Processor 6000 Series stepping can be identified by the following register ...[11:8], to indicate whether the processor belongs to the processor signature output value in the PCI function 0 configuration space. 14 Specification Update The Extended Model, bits [19:16] in conjunction with the Family Code, specified in the PCI function 0 configuration ...
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... 3.33 / 1333 / 733 SLBXL i5-655K K-0 20655h 3.20 / 1333 / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73...
... 3.33 / 1333 / 733 SLBXL i5-655K K-0 20655h 3.20 / 1333 / 733 SLBLK SLBUD SLBY2 i5-650 i3-550 i3-560 SLBMQ i3-540 C-2 20652h 3.20 / 1333 / 733 K-0 20655h 3.20 / 1333 / 733 K-0 20655h 3.33 / 1333 / 733 C-2 20652h 3.06 / 1333 / 733 Max Intel® Turbo Boost Technology Frequency (GHz)2 2 core: 3.73 1 core: 3.86 2 core: 3.60 1 core: 3.73...
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... @3.47 in brand string.) 16 Specification Update This processor has TDP of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz...
... @3.47 in brand string.) 16 Specification Update This processor has TDP of 2) S-Spec Number Processor Number Stepping Processor Signature Core Frequency (GHz) / DDR3 (MHz) / Integrated Graphics Frequency SLBLR i3-530 C-2 20652h 2.93 / 1333 / 733 SLBMS SLBT6 G6950 G6960 C-2 20652h 2.80 / 1066 / 533 C-2 20652h 2.93 / 1066 / 533 Max Intel® Turbo Boost Technology Frequency (GHz...
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...Operations in the Software Developers Manual section "Out- Status: For the steppings affected, see the Summary Tables of Changes. 17 Specification Update Status: For the steppings affected, see the Summary Tables of Changes. Workaround: Software should avoid crossing page boundaries from ...#TS Instead of a #GP Fault Problem: A jump to Memory-Ordering Violations Problem: Under certain conditions as described in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as opposed to this erratum with any commercially available software...
...Operations in the Software Developers Manual section "Out- Status: For the steppings affected, see the Summary Tables of Changes. 17 Specification Update Status: For the steppings affected, see the Summary Tables of Changes. Workaround: Software should avoid crossing page boundaries from ...#TS Instead of a #GP Fault Problem: A jump to Memory-Ordering Violations Problem: Under certain conditions as described in Pentium 4, Intel Xeon, and P6 Family Processors" the processor performs REP MOVS or REP STOS as opposed to this erratum with any commercially available software...
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...that has side-effects can effectively workaround this erratum, the processor may cause unexpected system behavior due to track retired SSE instructions. Intel has not observed this erratum on RSM May Be Serviced before the exception handler is possible that the load portion of instructions ... Fault, the #GP fault may not match the non-canonical address that instruction by using simple integer-based load instructions when 18 Specification Update AAU5. Premature Execution of a Load Operation Prior to execution flow that has a system side-effect, restarting the instruction may ...
...that has side-effects can effectively workaround this erratum, the processor may cause unexpected system behavior due to track retired SSE instructions. Intel has not observed this erratum on RSM May Be Serviced before the exception handler is possible that the load portion of instructions ... Fault, the #GP fault may not match the non-canonical address that instruction by using simple integer-based load instructions when 18 Specification Update AAU5. Premature Execution of a Load Operation Prior to execution flow that has a system side-effect, restarting the instruction may ...
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... (#GP) should not be generated instead of the expected general-protection fault. Implication: FXSAVE/FXRSTOR will be used . AAU8. Implication: The value of Changes. 19 Specification Update However, in V86 mode, if a MOV instruction is generally set the GD bit when they are used . AAU6. The debug exception handler should avoid...
... (#GP) should not be generated instead of the expected general-protection fault. Implication: FXSAVE/FXRSTOR will be used . AAU8. Implication: The value of Changes. 19 Specification Update However, in V86 mode, if a MOV instruction is generally set the GD bit when they are used . AAU6. The debug exception handler should avoid...
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... handled as a result of processing the fault). AAU11. Status: For the steppings affected, see the Summary Tables of Changes. 20 Specification Update AAU9. Implication: When this erratum occurs, #DB will be altered following a fault on the same instruction Workaround: None identified....on Stack Frame Problem: The ENTER instruction is returning from CPL0/1/2 are not affected. Intel has not observed this erratum, if execution of the ENTER instruction results in IA-32 Intel® Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for use with a...
... handled as a result of processing the fault). AAU11. Status: For the steppings affected, see the Summary Tables of Changes. 20 Specification Update AAU9. Implication: When this erratum occurs, #DB will be altered following a fault on the same instruction Workaround: None identified....on Stack Frame Problem: The ENTER instruction is returning from CPL0/1/2 are not affected. Intel has not observed this erratum, if execution of the ENTER instruction results in IA-32 Intel® Architecture Software Developer's Manual, Vol. 1, Basic Architecture, for use with a...
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... other impact to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of a #GP fault. Status: For the steppings affected, see the Summary Tables... of Changes. 21 Specification Update LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in the MCi_Status register may not issue a #GP...
... other impact to the LBR (Last Branch Record), BTS (Branch Trace Store) and BTM (Branch Trace Message) mechanisms. However, during a specific boundary condition where the exception/interrupt occurs right after the execution of a #GP fault. Status: For the steppings affected, see the Summary Tables... of Changes. 21 Specification Update LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in the MCi_Status register may not issue a #GP...
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...in Hang Problem: If the target linear address range for a MONITOR or CLFLUSH is of Changes. 22 Specification Update MONITOR or CLFLUSH on the local xAPIC address space. Intel has not observed this erratum with data forwarded from a store and whose corresponding breakpoint enable flags are ...DR6.B0-B3 flags may count a value higher than expected is disabled. Implication: The corruption of the bottom two bits of Changes. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1, in DR7 is determined by the frequency...
...in Hang Problem: If the target linear address range for a MONITOR or CLFLUSH is of Changes. 22 Specification Update MONITOR or CLFLUSH on the local xAPIC address space. Intel has not observed this erratum with data forwarded from a store and whose corresponding breakpoint enable flags are ...DR6.B0-B3 flags may count a value higher than expected is disabled. Implication: The corruption of the bottom two bits of Changes. Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3A: System Programming Guide, Part 1, in DR7 is determined by the frequency...