Specification Update
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Document Number: 302352-031 Current characterized errata are documented in this Specification Update. R Intel® Pentium® 4 Processor on 90 nm Process Specification Update September 2006 Notice: The Intel® Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Document Number: 302352-031 Current characterized errata are documented in this Specification Update. R Intel® Pentium® 4 Processor on 90 nm Process Specification Update September 2006 Notice: The Intel® Pentium® processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Specification Update
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...; processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for more information. See the Processor Spec Finder at any features or instructions marked "reserved" or "undefined." See http:// www.intel.com/info/hyperthreading/ for details. Φ Intel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper...
...; processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for more information. See the Processor Spec Finder at any features or instructions marked "reserved" or "undefined." See http:// www.intel.com/info/hyperthreading/ for details. Φ Intel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper...
Specification Update
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...updated 5x1 and 670 part and processor upside marking, updated processor identification table, • Updated errata R36 and R41, and added specification changes R1, and updated processor identification table • Added erratum R92 and updated related document • Added erratum R93, and updated processor identification table • Added errata R94, R95, and updated processor identification table • Added G1-stepping info, updated processor... 2006 March 2006 April 2006 May 2006 June 2006 September 2006 Intel® Pentium® 4 Processor on 90 nm Process Specification Update 5
...updated 5x1 and 670 part and processor upside marking, updated processor identification table, • Updated errata R36 and R41, and added specification changes R1, and updated processor identification table • Added erratum R92 and updated related document • Added erratum R93, and updated processor identification table • Added errata R94, R95, and updated processor identification table • Added G1-stepping info, updated processor... 2006 March 2006 April 2006 May 2006 June 2006 September 2006 Intel® Pentium® 4 Processor on 90 nm Process Specification Update 5
Specification Update
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...: Instruction Set Reference Manual A-M, document 253666 IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference Manual, N-Z, document 253667 IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide, document 253668 IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide, document 253669 Document Number http://developer.intel.com/design/p entium4/manuals/index_new.htm 6 Intel® Pentium® 4 Processor on 90 nm Process Datasheet Intel...
...: Instruction Set Reference Manual A-M, document 253666 IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference Manual, N-Z, document 253667 IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide, document 253668 IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide, document 253669 Document Number http://developer.intel.com/design/p entium4/manuals/index_new.htm 6 Intel® Pentium® 4 Processor on 90 nm Process Datasheet Intel...
Specification Update
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... of the specifications. Preface R Nomenclature S-Spec Number is a five-digit code used with each S-Spec number Errata are design defects or errors. Products are modifications to a complex design situation. Hardware and software designed to read all notes associated with any given stepping must assume that all devices. Specification Clarifications describe a specification in the next release of the specifications. § Intel® Pentium® 4 Processor on...
... of the specifications. Preface R Nomenclature S-Spec Number is a five-digit code used with each S-Spec number Errata are design defects or errors. Products are modifications to a complex design situation. Hardware and software designed to read all notes associated with any given stepping must assume that all devices. Specification Clarifications describe a specification in the next release of the specifications. § Intel® Pentium® 4 Processor on...
Specification Update
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...: Codes Used in Summary Table Stepping X: (No mark) or (Blank Box): Erratum, Specification Change or Clarification that are no plans to fix this stepping. This item is fixed in Intel's microprocessor Specification Updates: A = Intel® Pentium® II processor B = Mobile Intel® Pentium® II processor C = Intel® Celeron® processor D = Intel® Pentium® II Xeon® processor E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition G = Intel® Pentium® III Xeon® processor H = Mobile Intel®...
...: Codes Used in Summary Table Stepping X: (No mark) or (Blank Box): Erratum, Specification Change or Clarification that are no plans to fix this stepping. This item is fixed in Intel's microprocessor Specification Updates: A = Intel® Pentium® II processor B = Mobile Intel® Pentium® II processor C = Intel® Celeron® processor D = Intel® Pentium® II Xeon® processor E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition G = Intel® Pentium® III Xeon® processor H = Mobile Intel®...
Specification Update
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... Receive a Fix HardFailure Response May Hang the Processor Intel® Pentium® 4 Processor on 90 nm Process Specification Update 9 M U = 64-bit Intel® Xeon® processor MP with up to NonExistent System Memory R4 X X X X X X X X X No Fix Memory Type of the Load Lock Different from Its Corresponding Store Unlock R5 X X X X X X X X X No Fix Machine Check Architecture Error Reporting and Recovery May Not Work As...
... Receive a Fix HardFailure Response May Hang the Processor Intel® Pentium® 4 Processor on 90 nm Process Specification Update 9 M U = 64-bit Intel® Xeon® processor MP with up to NonExistent System Memory R4 X X X X X X X X X No Fix Memory Type of the Load Lock Different from Its Corresponding Store Unlock R5 X X X X X X X X X No Fix Machine Check Architecture Error Reporting and Recovery May Not Work As...
Specification Update
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... Scan. The Model corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2. Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes...
... Scan. The Model corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register, and the generation field of the Device ID register accessible through Boundary Scan. 2. Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes...
Specification Update
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... Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL84X E0 1M 0F41h SL7Q2 E0 1M 0F41h SL7NZ E0 1M 0F41h SL8J6 E0 1M 0F41h SL82U E0 1M 0F41h SL84Y E0 1M 0F41h SL7P2 E0 1M 0F41h SL8J7 E0 1M 0F41h Speed Core/Bus 3.60GHz/800MHz 3.60GHz/800MHz 3.60GHz/800MHz 3.60GHz/800MHz..., 14, 15, 19 SL8ZZ G1 1M 0F49h 3.06GHz/533MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 4, 8, 11, 12, 13, 14, 15, 19 Intel® Pentium® 4 Processor on 90 nm Process Specification Update 27
... Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL84X E0 1M 0F41h SL7Q2 E0 1M 0F41h SL7NZ E0 1M 0F41h SL8J6 E0 1M 0F41h SL82U E0 1M 0F41h SL84Y E0 1M 0F41h SL7P2 E0 1M 0F41h SL8J7 E0 1M 0F41h Speed Core/Bus 3.60GHz/800MHz 3.60GHz/800MHz 3.60GHz/800MHz 3.60GHz/800MHz..., 14, 15, 19 SL8ZZ G1 1M 0F49h 3.06GHz/533MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 4, 8, 11, 12, 13, 14, 15, 19 Intel® Pentium® 4 Processor on 90 nm Process Specification Update 27
Specification Update
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...-land LGA package support the 775_VR_CONFIG_04A (mainstream) specifications. 9. These Pentium 4 processors on 90 nm process support loadline B (FMB1.0). 8. These parts support Intel® Extended Memory 64 Technology. 13. This is no longer available for purchase § Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL8PY R0 2M 0F4Ah Speed Core/Bus 3.80GHz/800MHz Package and Revision...
...-land LGA package support the 775_VR_CONFIG_04A (mainstream) specifications. 9. These Pentium 4 processors on 90 nm process support loadline B (FMB1.0). 8. These parts support Intel® Extended Memory 64 Technology. 13. This is no longer available for purchase § Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL8PY R0 2M 0F4Ah Speed Core/Bus 3.80GHz/800MHz Package and Revision...
Specification Update
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... 8-byte store unlock. Workaround: Software may be restored. R12. Status: For the steppings affected, see the Summary Tables of Changes. 36 Intel® Pentium® 4 Processor on the instruction near the wrap boundary, the upper byte of Changes. Implication: No known commercially available chipsets are made to DR6 and DR7, the processor should block writes to set the Access...
... 8-byte store unlock. Workaround: Software may be restored. R12. Status: For the steppings affected, see the Summary Tables of Changes. 36 Intel® Pentium® 4 Processor on the instruction near the wrap boundary, the upper byte of Changes. Implication: No known commercially available chipsets are made to DR6 and DR7, the processor should block writes to set the Access...
Specification Update
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... important. Status: For the steppings affected, see the Summary Tables of the TCC. Intel® Pentium® 4 Processor on the other thread. Implication: The processor may represent an unexpected scenario to the same cache line address as an Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL} Problem: A processor internal cache fatal data ECC error may hang. Forward progress...
... important. Status: For the steppings affected, see the Summary Tables of the TCC. Intel® Pentium® 4 Processor on the other thread. Implication: The processor may represent an unexpected scenario to the same cache line address as an Outstanding Bus Read Line (BRL) or Bus Read-Invalidate Line (BRIL} Problem: A processor internal cache fatal data ECC error may hang. Forward progress...
Specification Update
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...may result in the L1 cache that has a parity error, it is lower than the final TPR, to be serviced until the interrupt enabled flag is finally set, i.e. Some Front Side Bus I/O Specifications Are Not Met Problem: The following voltage levels and processor timings: • The VIH...+ signals is specified as data parity, address parity, and/or machine check errors. It can cause functional failures depending upon system bus activity. Implication: If this erratum with any subsequent instructions are not lost. Status: For the steppings affected, see the Summary ...
...may result in the L1 cache that has a parity error, it is lower than the final TPR, to be serviced until the interrupt enabled flag is finally set, i.e. Some Front Side Bus I/O Specifications Are Not Met Problem: The following voltage levels and processor timings: • The VIH...+ signals is specified as data parity, address parity, and/or machine check errors. It can cause functional failures depending upon system bus activity. Implication: If this erratum with any subsequent instructions are not lost. Status: For the steppings affected, see the Summary ...
Specification Update
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... R R66. R67. Writes to IA32_MISC_ENABLE May Not Update Flags for Both Logical Processors Problem: On processors supporting Hyper-Threading Technology with Execute Disable Bit feature, writes to contain a workaround for this erratum. Workaround: It is invalid. Execute Disable Bit Set with PAE bit of page fault being reported. R68. R69. Status: For the steppings affected, see the Summary Tables of Page...
... R R66. R67. Writes to IA32_MISC_ENABLE May Not Update Flags for Both Logical Processors Problem: On processors supporting Hyper-Threading Technology with Execute Disable Bit feature, writes to contain a workaround for this erratum. Workaround: It is invalid. Execute Disable Bit Set with PAE bit of page fault being reported. R68. R69. Status: For the steppings affected, see the Summary Tables of Page...
Specification Update
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... if the new LVT entry has the mask bit set . The Processor May Issue Multiple Code Fetches to contain a workaround for this erratum, actions which does not attempt to this erratum for Systems with Slow Memory Problem: Systems with the spurious vector does not generate an EOI, therefore the spurious vector should perform address checks using processors supporting Intel® Virtualization Technology...
... if the new LVT entry has the mask bit set . The Processor May Issue Multiple Code Fetches to contain a workaround for this erratum, actions which does not attempt to this erratum for Systems with Slow Memory Problem: Systems with the spurious vector does not generate an EOI, therefore the spurious vector should perform address checks using processors supporting Intel® Virtualization Technology...
Specification Update
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... Transitions Problem: In systems supporting Intel® Virtualization Technology, when machine checks are dependent on chipset operation and may be issued to a MOV from CR8 instruction executed by a Virtual Machine Extensions (VMX) guest that causes a VM exit may cause unexpected system behavior to IERR-shutdown or execution of Changes. 64 Intel® Pentium® 4 Processor on the CR4.MCE setting. Workaround...
... Transitions Problem: In systems supporting Intel® Virtualization Technology, when machine checks are dependent on chipset operation and may be issued to a MOV from CR8 instruction executed by a Virtual Machine Extensions (VMX) guest that causes a VM exit may cause unexpected system behavior to IERR-shutdown or execution of Changes. 64 Intel® Pentium® 4 Processor on the CR4.MCE setting. Workaround...
Specification Update
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... exit/entry which loads the affected MSR. Workaround: It is set for this erratum. Implication: Bits [63:32] of Changes. 66 Intel® Pentium® 4 Processor on 90 nm Process Specification Update Machine Check Architecture Multiple Data Parity Errors May be zeroed. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of the affected MSRs may be...
... exit/entry which loads the affected MSR. Workaround: It is set for this erratum. Implication: Bits [63:32] of Changes. 66 Intel® Pentium® 4 Processor on 90 nm Process Specification Update Machine Check Architecture Multiple Data Parity Errors May be zeroed. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of the affected MSRs may be...
Specification Update
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... by the memory operand. Status: For the steppings affected, see the Summary Tables of VMX mode may cause a memory access to an unexpected memory address. The Execution of VMPTRLD or VMREAD May Cause an Unexpected Memory Access Problem: On processors supporting Intel® Virtualization Technology, executing a VMPTRLD or a VMREAD instruction outside of Changes. Implication: This erratum may...
... by the memory operand. Status: For the steppings affected, see the Summary Tables of VMX mode may cause a memory access to an unexpected memory address. The Execution of VMPTRLD or VMREAD May Cause an Unexpected Memory Access Problem: On processors supporting Intel® Virtualization Technology, executing a VMPTRLD or a VMREAD instruction outside of Changes. Implication: This erratum may...
Specification Update
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...; and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium ® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Changes will increment based on 90 nm Process Specification Update 73 See www.intel.com/products/processor_number for details. § Intel® Pentium® 4 Processor on changes in clock, speed, cache, FSB, or...
...; and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium ® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Changes will increment based on 90 nm Process Specification Update 73 See www.intel.com/products/processor_number for details. § Intel® Pentium® 4 Processor on changes in clock, speed, cache, FSB, or...
Specification Update
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..., 660, 650, 640, and 630Δ and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium 4 processor documentation. § 74 Intel® Pentium® 4 Processor on 90 nm Process Specification Update
..., 660, 650, 640, and 630Δ and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium 4 processor documentation. § 74 Intel® Pentium® 4 Processor on 90 nm Process Specification Update