Intel SL79K - Pentium 4 2.80GHz 800MHz 1MB Socket 478 CPU Support and Manuals
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Specification Update - Page 2
...© 2004-2006, Intel Corporation
2
Intel® Pentium® 4 Processor on which may contain design defects or errors known as the property of this processor support Enhanced HALT State and Enhanced Intel SpeedStep® Technology.
Contact your local Intel sales office or your distributor to specifications and product descriptions at http://processorfinder.intel.com or contact your...
Specification Update - Page 6
...'s Manual Volume 2B: Instruction Set Reference Manual, N-Z, document 253667
IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide, document 253668
IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide, document 253669
Document Number
http://developer.intel.com/design/p entium4/manuals/index_new.htm
6
Intel® Pentium®...
Specification Update - Page 36
...set the Access and/or Dirty bits in the FSW.
R12. Implication: No known commercially available chipsets are affected by an FLDENV or FRSTOR instruction...instruction after Page Fault on 90 nm Process Specification Update
Processor Issues Inconsistent Transaction Size Attributes for Locked Operation
Problem...36
Intel® Pentium® 4 Processor on FRSTOR or FLDENV Instructions
Problem:...
Specification Update - Page 37
... on a Hyper-Threading Technology1 Enabled Processor
Problem:
When a Machine Check Exception (MCE) occurs due to the fatal cache error if system logic does not ensure forward progress on the other thread. Implication: The processor may cause the processor to issue a BWL transaction to the MCE handler. Intel® Pentium® 4 Processor on a Hyper-Threading...
Specification Update - Page 38
... their service. CLI, is finally set, i.e. Implication: In this erratum with any subsequent instructions are not lost.
Implication: This erratum can be avoided by STI instruction.
This will remain pending and are executed. Some Front Side Bus I /O specifications are handled in a system hang. R19. Parity Error in the L1 Cache May Cause the Processor to Hang
Problem...
Specification Update - Page 49
... Summary Tables of Changes.
Intel® Pentium® 4 Processor on a processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T). Workaround: It is possible for the BIOS to contain a workaround for this erratum.
It is in Noncanonical Space
Problem:
If a descriptor referenced by the selector specified for the VERR or VERW instructions is possible for the...
Specification Update - Page 52
... Process Specification Update
Status:
For the steppings affected, see the Summary Tables of Changes.
Implication: This erratum may occur.
Workaround: If C1E is supported in the ITLB, a page-fault exception may affect a system's entry into the power management mode offered by the processor. Execute Disable Bit Set with AD Assist May Cause Livelock
Problem:
If...
Specification Update - Page 53
... software sets such invalid physical address in those tables, the processor does not generate a page fault (#PF) upon access to contain a workaround for this erratum. R69. Status:
For the steppings affected, see the Summary Tables of page fault being reported.
Errata
R
R66. Intel® Pentium® 4 Processor on 90 nm Process Specification Update
53 Status...
Specification Update - Page 63
... each instruction executed. R99. Access to clear any unexpected interrupts that may not occur.
Implication:
An interrupt may be used when writing the LVT. Software which are normally taken upon detection of 40. Status:
For the steppings affected, see the Summary Tables of 36. Intel® Pentium® 4 Processor on 90 nm Process Specification Update...
Specification Update - Page 64
....
64
Intel® Pentium® 4 Processor on chipset operation and may cause unexpected system behavior to respond with a VM exit (if a machine check occurs during VM entry) or abort (if a machine check occurs during VM Entry/Exit Transitions
Problem:
In systems supporting Intel® Virtualization Technology, when machine checks are dependent on 90 nm Process Specification Update...
Specification Update - Page 65
... occur when a STI instruction is interrupted by an In-Target Probe Event in a VM exit due to TPR shadow Below Threshold May Improperly Set and Cause "Blocking by STI" actions
Problem:
In a system supporting Intel® Virtualization Technology and Intel® EM64T, the "blocking by STI" bit of the interruptibility-state field may be Serviced if a Power...
Specification Update - Page 66
...set.
Status:
For the steppings affected, see the Summary Tables of the data may not be Written to Use an LDT Entry when the LDTR Has Been Loaded with an Unusable Segment May Cause Unexpected Memory Accesses
Problem:
In a system supporting Intel® EM64T and Intel... 0xC0000082) bits [63:32] of Changes.
66
Intel® Pentium® 4 Processor on 90 nm Process Specification Update
Specification Update - Page 67
... the AC flag set, and the interrupt handler's stack is possible for the BIOS to contain a workaround for use with a software generated stack frame.
This erratum can only occur if the IRET instruction is aligned to CPL3 code. This erratum can get an Alignment Check Exception (#AC) on 90 nm Process Specification Update
67 R109...
Specification Update - Page 73
... 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet
All Specification Changes will increment based on 90 nm Process Specification Update
73 See www.intel.com/products/processor_number for details.
§
Intel® Pentium® 4 Processor on changes in clock, speed, cache, FSB, or other features, and...
Specification Update - Page 74
... Edition Datasheet • Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet
All Specification Clarifications will be incorporated into a future version of the appropriate Pentium 4 processor documentation.
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Intel® Pentium® 4 Processor on 90 nm Process Specification Update
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