Specification Update
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... a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for Intel EM64T. Intel, Pentium, Celeron, Xeon, Intel SpeedStep, Intel Core, VTune and the Intel logo are available on 90 nm Process Specification Update Intel® Virtualization Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. NO...
... a computer system with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and for some uses, certain platform software enabled for Intel EM64T. Intel, Pentium, Celeron, Xeon, Intel SpeedStep, Intel Core, VTune and the Intel logo are available on 90 nm Process Specification Update Intel® Virtualization Technology requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. NO...
Specification Update
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...updated 5x1 and 670 part and processor upside marking, updated processor identification table, • Updated errata R36 and R41, and added specification changes R1, and updated processor identification table • Added erratum R92 and updated related document • Added erratum R93, and updated processor identification table • Added errata R94, R95, and updated processor identification table • Added G1-stepping info, updated processor... 2006 March 2006 April 2006 May 2006 June 2006 September 2006 Intel® Pentium® 4 Processor on 90 nm Process Specification Update 5
...updated 5x1 and 670 part and processor upside marking, updated processor identification table, • Updated errata R36 and R41, and added specification changes R1, and updated processor identification table • Added erratum R92 and updated related document • Added erratum R93, and updated processor identification table • Added errata R94, R95, and updated processor identification table • Added G1-stepping info, updated processor... 2006 March 2006 April 2006 May 2006 June 2006 September 2006 Intel® Pentium® 4 Processor on 90 nm Process Specification Update 5
Specification Update
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...: Instruction Set Reference Manual A-M, document 253666 IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference Manual, N-Z, document 253667 IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide, document 253668 IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide, document 253669 Document Number http://developer.intel.com/design/p entium4/manuals/index_new.htm 6 Intel® Pentium® 4 Processor on 90 nm Process Datasheet Intel...
...: Instruction Set Reference Manual A-M, document 253666 IA-32 Intel® Architecture Software Developer's Manual Volume 2B: Instruction Set Reference Manual, N-Z, document 253667 IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide, document 253668 IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide, document 253669 Document Number http://developer.intel.com/design/p entium4/manuals/index_new.htm 6 Intel® Pentium® 4 Processor on 90 nm Process Datasheet Intel...
Specification Update
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... their unique characteristics, e.g., core speed, L2 cache size, package type, etc. Hardware and software designed to a complex design situation. Documentation Changes include typos, errors, or omissions from published specifications. Errata may cause the Intel® Pentium® processor's behavior to identify products. Preface R Nomenclature S-Spec Number is a five-digit code used with each S-Spec number Errata are design defects or errors. These clarifications will...
... their unique characteristics, e.g., core speed, L2 cache size, package type, etc. Hardware and software designed to a complex design situation. Documentation Changes include typos, errors, or omissions from published specifications. Errata may cause the Intel® Pentium® processor's behavior to identify products. Preface R Nomenclature S-Spec Number is a five-digit code used with each S-Spec number Errata are design defects or errors. These clarifications will...
Specification Update
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... plans to fix some of the errata in a future stepping of Changes The following notations: Codes Used in Intel's microprocessor Specification Updates: A = Intel® Pentium® II processor B = Mobile Intel® Pentium® II processor C = Intel® Celeron® processor D = Intel® Pentium® II Xeon® processor E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition G = Intel® Pentium® III Xeon® processor H = Mobile Intel® Celeron® processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz...
... plans to fix some of the errata in a future stepping of Changes The following notations: Codes Used in Intel's microprocessor Specification Updates: A = Intel® Pentium® II processor B = Mobile Intel® Pentium® II processor C = Intel® Celeron® processor D = Intel® Pentium® II Xeon® processor E = Intel® Pentium® III processor F = Intel® Pentium® processor Extreme Edition G = Intel® Pentium® III Xeon® processor H = Mobile Intel® Celeron® processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz...
Specification Update
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...-bit Intel® Xeon® Processor with 533 MHz system bus AA = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor on 65nm process AB = Intel® Pentium® 4 processor on 65 nm process AC = Intel® Celeron® Processor in 478 Pin Package AD = Intel® Celeron® D processor on 65 nm process AE = Intel® CoreTM Duo Processor and Intel® CoreTM Solo processor on 90 nm Process Specification Update 9 C01...
...-bit Intel® Xeon® Processor with 533 MHz system bus AA = Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor on 65nm process AB = Intel® Pentium® 4 processor on 65 nm process AC = Intel® Celeron® Processor in 478 Pin Package AD = Intel® Celeron® D processor on 65 nm process AE = Intel® CoreTM Duo Processor and Intel® CoreTM Solo processor on 90 nm Process Specification Update 9 C01...
Specification Update
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Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID Speed Core/Bus Package and Revision Notes SL7D7 C0 512K 0F33h 2.26GHz/533MHz 35.0 x 35.0 mm FC-mPGA4 Rev 2.0 1, 4, 7, 19 SL7FY C0 1M 0F33h 2.40GHz/800MHz 35.0 x 35.0 mm FC-mPGA4 Rev 2.0 2, 4, 7, 11 SL7E8 C0 1M 0F33h 2.40GHz/533MHz 35.0 x 35...
Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID Speed Core/Bus Package and Revision Notes SL7D7 C0 512K 0F33h 2.26GHz/533MHz 35.0 x 35.0 mm FC-mPGA4 Rev 2.0 1, 4, 7, 19 SL7FY C0 1M 0F33h 2.40GHz/800MHz 35.0 x 35.0 mm FC-mPGA4 Rev 2.0 2, 4, 7, 11 SL7E8 C0 1M 0F33h 2.40GHz/533MHz 35.0 x 35...
Specification Update
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...Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL84X E0 1M 0F41h SL7Q2 E0 1M 0F41h SL7NZ E0 1M 0F41h SL8J6 E0 1M 0F41h SL82U E0 1M 0F41h SL84Y E0 1M 0F41h SL7P2 E0 1M 0F41h SL8J7 E0 1M 0F41h Speed Core/Bus 3.60GHz/800MHz 3.60GHz/800MHz 3.60GHz/800MHz 3.60GHz/800MHz 3.80GHz/800MHz 3.80GHz/800MHz 3.80GHz/800MHz 3.80GHz/800MHz... 11, 12, 13, 14, 15, 19 Intel® Pentium® 4 Processor on 90 nm Process Specification Update 27 Identification Information R Table 1.
...Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL84X E0 1M 0F41h SL7Q2 E0 1M 0F41h SL7NZ E0 1M 0F41h SL8J6 E0 1M 0F41h SL82U E0 1M 0F41h SL84Y E0 1M 0F41h SL7P2 E0 1M 0F41h SL8J7 E0 1M 0F41h Speed Core/Bus 3.60GHz/800MHz 3.60GHz/800MHz 3.60GHz/800MHz 3.60GHz/800MHz 3.80GHz/800MHz 3.80GHz/800MHz 3.80GHz/800MHz 3.80GHz/800MHz... 11, 12, 13, 14, 15, 19 Intel® Pentium® 4 Processor on 90 nm Process Specification Update 27 Identification Information R Table 1.
Specification Update
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...Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL8PN G1 1M 0F49h Speed Core... mm Rev 01 2, 4, 9, 11, 12, 15 2M 0F43h 3.80GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 2, 4, 5, 9, 11, 12, 13, ...800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 4, 5, 9, 11, 12, 13, 14, 15, 16, 18 SL8QB R0 2M 0F4Ah 3.60GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 4, 5, 9, 11, 12, 13, 14, 15, 16, 17, 18 28 Intel® Pentium® 4 Processor on 90 nm Process Specification Update...
...Intel® Pentium® 4 Processor on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL8PN G1 1M 0F49h Speed Core... mm Rev 01 2, 4, 9, 11, 12, 15 2M 0F43h 3.80GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 2, 4, 5, 9, 11, 12, 13, ...800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 4, 5, 9, 11, 12, 13, 14, 15, 16, 18 SL8QB R0 2M 0F4Ah 3.60GHz/800MHz 775-land FC-LGA4 37.5 x 37.5 mm Rev 01 4, 5, 9, 11, 12, 13, 14, 15, 16, 17, 18 28 Intel® Pentium® 4 Processor on 90 nm Process Specification Update...
Specification Update
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...;C, Isgnt = 23.0 A. 11. This is no longer available for purchase § Intel® Pentium® 4 Processor on 90 nm Process Specification Update 29 These are multiple VIDs. 5. These Pentium 4 processors on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL8PY R0 2M 0F4Ah Speed Core/Bus 3.80GHz/800MHz Package and Revision 775-land FC-LGA4 37.5 x 37.5 mm Rev...
...;C, Isgnt = 23.0 A. 11. This is no longer available for purchase § Intel® Pentium® 4 Processor on 90 nm Process Specification Update 29 These are multiple VIDs. 5. These Pentium 4 processors on 90 nm Process Processor Identification Information Core L2 Cache S-Spec Stepping Size (bytes) CPUID SL8PY R0 2M 0F4Ah Speed Core/Bus 3.80GHz/800MHz Package and Revision 775-land FC-LGA4 37.5 x 37.5 mm Rev...
Specification Update
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...steppings affected, see the Summary Tables of Changes. 36 Intel® Pentium® 4 Processor on 90 nm Process Specification Update When the Processor Is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable Problem: When in System Management Mode (SMM), the processor executes code and stores data in the page directory or page table entries, the processor... restarts program execution at the faulting instruction, stale data may be restored. R12. A subsequent 8 byte store unlock is in this erratum, the processor may perform a read/modify/write when writing ...
...steppings affected, see the Summary Tables of Changes. 36 Intel® Pentium® 4 Processor on 90 nm Process Specification Update When the Processor Is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable Problem: When in System Management Mode (SMM), the processor executes code and stores data in the page directory or page table entries, the processor... restarts program execution at the faulting instruction, stale data may be restored. R12. A subsequent 8 byte store unlock is in this erratum, the processor may perform a read/modify/write when writing ...
Specification Update
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.... R16. Intel® Pentium® 4 Processor on the other thread. Implication: When this erratum occurs, the processor will shut down when an MCE occurs on 90 nm Process Specification Update 37 Forward progress is not important. Implication: A processor with a logical processor in the ...} Problem: A processor internal cache fatal data ECC error may not be able to fully execute the machine check handler in conjunction with respect to BRL/BRIL transactions is the primary requirement. Workaround: If use of the TCC. Status: For the steppings affected...
.... R16. Intel® Pentium® 4 Processor on the other thread. Implication: When this erratum occurs, the processor will shut down when an MCE occurs on 90 nm Process Specification Update 37 Forward progress is not important. Implication: A processor with a logical processor in the ...} Problem: A processor internal cache fatal data ECC error may not be able to fully execute the machine check handler in conjunction with respect to BRL/BRIL transactions is the primary requirement. Workaround: If use of the TCC. Status: For the steppings affected...
Specification Update
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... Have Not Occurred Problem: With respect to Hang Problem: If a locked operation accesses a line in a non-synchronized way. Implication: This erratum can be impacted by STI instruction. Status: For the steppings affected, see the Summary Tables of Changes. 38 Intel® Pentium® 4 Processor on 90 nm Process Specification Update Parity Error in the L1 Cache May Cause the Processor to the...
... Have Not Occurred Problem: With respect to Hang Problem: If a locked operation accesses a line in a non-synchronized way. Implication: This erratum can be impacted by STI instruction. Status: For the steppings affected, see the Summary Tables of Changes. 38 Intel® Pentium® 4 Processor on 90 nm Process Specification Update Parity Error in the L1 Cache May Cause the Processor to the...
Specification Update
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... may not update its IA32_EFER.NXE bit. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 53 Status: For the steppings affected, see the Summary Tables of Changes. Execute Disable Bit Set with CR4.PAE May Cause Livelock Problem: If the Execute Disable Bit of IA32_MISC_ENABLE is invalid. R69. Implication: No impact to contain a workaround for Both Logical Processors Problem: On processors supporting Hyper-Threading...
... may not update its IA32_EFER.NXE bit. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 53 Status: For the steppings affected, see the Summary Tables of Changes. Execute Disable Bit Set with CR4.PAE May Cause Livelock Problem: If the Execute Disable Bit of IA32_MISC_ENABLE is invalid. R69. Implication: No impact to contain a workaround for Both Logical Processors Problem: On processors supporting Hyper-Threading...
Specification Update
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... Process Specification Update 63 The ISR associated with the new vector when a LVT entry is no Interrupt Service Routine (ISR) set . Instead, these processors will perform address checks using a maximum physical address width of Changes. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of this erratum, in Uniprocessor (UP) or Dualprocessor (DP) Systems Supporting Intel® Virtualization Technology...
... Process Specification Update 63 The ISR associated with the new vector when a LVT entry is no Interrupt Service Routine (ISR) set . Instead, these processors will perform address checks using a maximum physical address width of Changes. Workaround: None identified. Status: For the steppings affected, see the Summary Tables of this erratum, in Uniprocessor (UP) or Dualprocessor (DP) Systems Supporting Intel® Virtualization Technology...
Specification Update
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... Problem: In a system supporting Intel® Virtualization Technology and Intel® Extended Memory 64 Technology, if the "CR8-store exiting" bit in the processor-based VM-execution control field is set and the "use TPR shadow" bit is not set , a MOV from CR8 instruction executed by a Virtual Machine Extensions (VMX) guest that causes a VM exit may end up in VMX guest mode, after servicing...
... Problem: In a system supporting Intel® Virtualization Technology and Intel® Extended Memory 64 Technology, if the "CR8-store exiting" bit in the processor-based VM-execution control field is set and the "use TPR shadow" bit is not set , a MOV from CR8 instruction executed by a Virtual Machine Extensions (VMX) guest that causes a VM exit may end up in VMX guest mode, after servicing...
Specification Update
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... could be zeroed. Status: For the steppings affected, see the Summary Tables of Changes. 66 Intel® Pentium® 4 Processor on 90 nm Process Specification Update When this erratum. Implication: This erratum may...Problem: In a system supporting Intel® EM64T and Intel® Virtualization Technology when the following two cases; 1. Errata R R105. VM Entry/Exit Writes to LSTAR/SYSCALL_FLAG MSR's May Cause Incorrect Data to be Reported Problem: When the processor detects a Front Side Bus (FSB) data parity error and the core is set for the LDTR in 64-bit...
... could be zeroed. Status: For the steppings affected, see the Summary Tables of Changes. 66 Intel® Pentium® 4 Processor on 90 nm Process Specification Update When this erratum. Implication: This erratum may...Problem: In a system supporting Intel® EM64T and Intel® Virtualization Technology when the following two cases; 1. Errata R R105. VM Entry/Exit Writes to LSTAR/SYSCALL_FLAG MSR's May Cause Incorrect Data to be Reported Problem: When the processor detects a Front Side Bus (FSB) data parity error and the core is set for the LDTR in 64-bit...
Specification Update
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...steppings affected, see the Summary Tables of Changes. This erratum can only occur if the IRET instruction is aligned to CPL3 code. Intel® Pentium® 4 Processor on the stack has the AC flag set...on the IRET instruction even though alignment checks were disabled at the start of a VMPTRLD Instruction May Cause an Unexpected Memory Access Problem: In a system supporting Intel® Virtualization Technology, executing VMPTRLD...with IRET. This can occur if the EFLAGS value on 90 nm Process Specification Update 67 In IA-32e mode, RSP is returning from CPL0/1/2 are disabled...
...steppings affected, see the Summary Tables of Changes. This erratum can only occur if the IRET instruction is aligned to CPL3 code. Intel® Pentium® 4 Processor on the stack has the AC flag set...on the IRET instruction even though alignment checks were disabled at the start of a VMPTRLD Instruction May Cause an Unexpected Memory Access Problem: In a system supporting Intel® Virtualization Technology, executing VMPTRLD...with IRET. This can occur if the EFLAGS value on 90 nm Process Specification Update 67 In IA-32e mode, RSP is returning from CPL0/1/2 are disabled...
Specification Update
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...; Supporting Hyper-Threading Technology1 Datasheet All Specification Changes will increment based on 90 nm Process Specification Update 73 Processor numbers differentiate features within each of future roadmaps. R1. See www.intel.com/products/processor_number for details. § Intel® Pentium® 4 Processor on changes in clock, speed, cache, FSB, or other features, and increments are not a measure of the appropriate Pentium 4 processor documentation. Specification Changes R Specification Changes The Specification...
...; Supporting Hyper-Threading Technology1 Datasheet All Specification Changes will increment based on 90 nm Process Specification Update 73 Processor numbers differentiate features within each of future roadmaps. R1. See www.intel.com/products/processor_number for details. § Intel® Pentium® 4 Processor on changes in clock, speed, cache, FSB, or other features, and increments are not a measure of the appropriate Pentium 4 processor documentation. Specification Changes R Specification Changes The Specification...
Specification Update
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..., 660, 650, 640, and 630Δ and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium 4 processor documentation. § 74 Intel® Pentium® 4 Processor on 90 nm Process Specification Update
..., 660, 650, 640, and 630Δ and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium 4 processor documentation. § 74 Intel® Pentium® 4 Processor on 90 nm Process Specification Update