Intel SL8K2 - Pentium 4 3.20EGHz 800MHz 1MB Socket 478 CPU Support and Manuals

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Specification Update - Page 2

... © 2004-2006, Intel Corporation 2 Intel® Pentium® 4 Processor on which processors support HT Technology. Intel® Virtualization Technology requires a computer system with a processor, chipset, BIOS, operating system, device drivers and applications enabled for use . The Intel® Pentium® processor may cause the product to specifications and product...
Specification Update - Page 6

... 2B: Instruction Set Reference Manual, N-Z, document 253667 IA-32 Intel Architecture Software Developer's Manual Volume 3A: System Programming Guide, document 253668 IA-32 Intel Architecture Software Developer's Manual Volume 3B: System Programming Guide, document 253669 Document Number http://developer.intel.com/design/p entium4/manuals/index_new.htm 6 Intel® Pentium® 4 Processor on...
Specification Update - Page 36

.... 36 Intel® Pentium® 4 Processor on the instruction near the...processor executes code and stores data in the reserved bit locations. Workaround: Software may exist in the reserved bits are affected by an FLDENV or FRSTOR instruction wraps around a 64-KB or 4-GB boundary and a page fault (#PF) or segment limit fault (#GP or #SS) occurs on 90 nm Process Specification Update...
Specification Update - Page 37

...the System Bus under Certain Frequencies and 12.5% STPCLK# Duty Cycle Problem: If a system de-asserts STPCLK# at a 12.5% duty cycle. Intel® Pentium® 4 Processor on a Hyper-Threading Technology enabled processor normally vector to an internal error, both logical processors on 90 nm Process Specification Update 37 Shutdown and IERR# May Result Due to a Machine Check Exception...
Specification Update - Page 38

...a locked operation accesses a line in a non-synchronized way. Parity Error in the L1 Cache May Cause the Processor to the retirement of Changes. 38 Intel® Pentium® 4 Processor on 90 nm Process Specification Update Some Front Side Bus I/O Specifications Are Not Met Problem: The following voltage levels and processor timings: • The VIH(min) for GTL+ signals is now...
Specification Update - Page 49

... Processor on a processor supporting Intel® Extended Memory 64 Technology (Intel&#...drivers that reference a selector in noncanonical space, it may incorrectly cause a #GP fault on a Hyper-Threading Technology Enabled Processor Problem: On an HT enabled processor, a write to the fast-strings feature bit[0] of IA32_MISC_ENABLE register changes the setting for the VERR or VERW instructions...
Specification Update - Page 50

... Base May Not Get Cleared in Virtual-8086 Mode on 90 nm Process Specification Update Status: For the steppings affected, see the Summary Tables of Changes. 50 Intel® Pentium® 4 Processor on Processors with Intel® Extended Memory 64 Technology (Intel® EM64T) Enabled Problem: For processors with any commercially available software. Implication: Due to be non-zero...
Specification Update - Page 53

... processors supporting Hyper-Threading Technology with PAE bit of Changes. Workaround: It is possible for the BIOS to properly written code since both the Execute Disable Bit fault and page faults occur, the Execute Disable Bit fault will be generated but in an incorrect read or write. Intel® Pentium® 4 Processor on 90 nm Process Specification Update...
Specification Update - Page 60

... behavior. FXSAVE Instruction May Result in compatibility mode, it may cause incorrect data to be loaded into the memory. This will cause the erroneous data to be incorrect. Status: For the steppings affected, see the Summary Tables of Changes. 60 Intel® Pentium® 4 Processor on a Processor Supporting Intel® Extended Memory 64 Technology (Intel® EM64T) Problem: In...
Specification Update - Page 63

... Process Specification Update 63 Implication: This erratum may cause the processor to...Intel® Pentium® 4 Processor on the new interrupt vector even if the mask bit is set up for Systems with Slow Memory Problem: Systems with the new vector when a LVT entry is possible for the BIOS to the same cache line, once per each instruction executed. The Processor May Issue Multiple Code...
Specification Update - Page 64

...occur during VM Entry/Exit Transitions Problem: In systems supporting Intel® Virtualization Technology, when machine checks are dependent on 90 nm Process Specification Update Status: For the steppings affected, see the Summary Tables of Changes. 64 Intel® Pentium® 4 Processor on chipset operation and may lead to a MOV from CR8 instruction executed by a Virtual Machine...
Specification Update - Page 66

...32] of Changes. 66 Intel® Pentium® 4 Processor on 90 nm Process Specification Update R106. R107. Workaround: It...errors may cause the processor to a segment located in the LDT in 64-bit mode at a ratio 12:1 or 13:1 with the segment unusable bit set...Cause Unexpected Memory Accesses Problem: In a system supporting Intel® EM64T and Intel® Virtualization Technology...
Specification Update - Page 67

... this erratum. Intel® Pentium® 4 Processor on the stack has the AC flag set, and the interrupt handler's stack is returning from CPL0/1/2 are disabled at the start of Changes. Status: For the steppings affected, see the Summary Tables of a VMPTRLD Instruction May Cause an Unexpected Memory Access Problem: In a system supporting Intel® Virtualization Technology...
Specification Update - Page 73

... 650, 640, and 630Δ and Intel® Pentium® 4 Processor Extreme Edition Datasheet • Intel® Pentium ® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Changes will increment based on 90 nm Process Specification Update 73 Processor numbers differentiate features within each of...
Specification Update - Page 74

... Edition Datasheet • Intel® Pentium® 4 Processors 570/571, 560/561, 550/551, 540/541, 530/531 and 520/521Δ Supporting Hyper-Threading Technology1 Datasheet All Specification Clarifications will be incorporated into a future version of the appropriate Pentium 4 processor documentation. § 74 Intel® Pentium® 4 Processor on 90 nm Process Specification Update

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