Specification Update
Page 38
...LBR/BTS/BTM will be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Errata Workaround...: None identified. Status: For the steppings affected, see the Summary Tables of the LBR, BTS, and BTM immediately after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU...
...LBR/BTS/BTM will be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Errata Workaround...: None identified. Status: For the steppings affected, see the Summary Tables of the LBR, BTS, and BTM immediately after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU...
Specification Update
Page 41
...of the Branch Instruction. INIT Does Not Clear Global Entries in the TLB Problem: INIT may incorrectly set by the CPU to MWAIT • In systems supporting Intel® Virtualization Technology a fault in protected mode with paging enabled and the page global enable flag is set to ...I/O read • An I/O read from an I /O instruction. • SMI is set (PGE bit of an IO operation that reads from an I /O port address. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 41 Specification Update
...of the Branch Instruction. INIT Does Not Clear Global Entries in the TLB Problem: INIT may incorrectly set by the CPU to MWAIT • In systems supporting Intel® Virtualization Technology a fault in protected mode with paging enabled and the page global enable flag is set to ...I/O read • An I/O read from an I /O instruction. • SMI is set (PGE bit of an IO operation that reads from an I /O port address. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 41 Specification Update
Specification Update
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... RSP is crossed. Status: For the steppings affected, see the Summary Tables of Changes. 46 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Errata AI65. IRET under the conditions given above, an IRET can...When the DTS (Digital Thermal Sensor) crosses one of VMLAUNCH/VMRESUME. Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is aligned to be observed with IRET. This erratum can get...
... RSP is crossed. Status: For the steppings affected, see the Summary Tables of Changes. 46 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Errata AI65. IRET under the conditions given above, an IRET can...When the DTS (Digital Thermal Sensor) crosses one of VMLAUNCH/VMRESUME. Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is aligned to be observed with IRET. This erratum can get...
