Specification Update
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.../products/processor_number for some uses. Δ Intel processor numbers are available on the absence or characteristics of others. The Intel® Core™2 Duo and Intel® Core™2 Extreme Processors may contain design defects or errors known as errata which processors support Intel 64, or consult with Intel® Virtualization Technology, an Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules...
.../products/processor_number for some uses. Δ Intel processor numbers are available on the absence or characteristics of others. The Intel® Core™2 Duo and Intel® Core™2 Extreme Processors may contain design defects or errors known as errata which processors support Intel 64, or consult with Intel® Virtualization Technology, an Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules...
Specification Update
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...; processor Dual-Core Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel...
...; processor Dual-Core Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel® Pentium® 4 processor Intel® Xeon® processor MP Intel...
Specification Update
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...Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect AI33 X X X Fixed Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction ... X X X No Fix Split Locked Stores May not Trigger the Monitoring Hardware AI37 X X Fixed REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 AI38 X X X X Fixed FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to...
...Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper 32 bits of 'From' Address Reported through BTMs or BTSs May be Incorrect AI33 X X X Fixed Unsynchronized Cross-Modifying Code Operations Can Cause Unexpected Instruction ... X X X No Fix Split Locked Stores May not Trigger the Monitoring Hardware AI37 X X Fixed REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 AI38 X X X X Fixed FXSAVE/FXRSTOR Instructions which Store to the End of the Segment and Cause a Wrap to...
Specification Update
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...64-bit Mode with Count Greater or Equal to 248 May Terminate Early REP MOVS/STOS Executing with Fast Strings Enabled and AI59 X X X X X No Fix Crossing Page Boundaries with EFLAGS.VM Set May Result in DR6 May be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo... Desktop Processor E6000 and E4000 Sequence 13 Specification Update Summary Tables of Changes NO B1 B2...
...64-bit Mode with Count Greater or Equal to 248 May Terminate Early REP MOVS/STOS Executing with Fast Strings Enabled and AI59 X X X X X No Fix Crossing Page Boundaries with EFLAGS.VM Set May Result in DR6 May be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo... Desktop Processor E6000 and E4000 Sequence 13 Specification Update Summary Tables of Changes NO B1 B2...
Specification Update
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...Invalidation Number DOCUMENTATION CHANGES - There are no Specification Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Number SPECIFICATION CLARIFICATIONS AI1 Clarification of Changes NO B1 B2 L2 M0 ...) are no Documentation Changes in IA-32e Mode May Not Produce a VMX Abort When Expected AI129 X X X X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results Number SPECIFICATION CHANGES -
...Invalidation Number DOCUMENTATION CHANGES - There are no Specification Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Number SPECIFICATION CLARIFICATIONS AI1 Clarification of Changes NO B1 B2 L2 M0 ...) are no Documentation Changes in IA-32e Mode May Not Produce a VMX Abort When Expected AI129 X X X X X No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results Number SPECIFICATION CHANGES -
Specification Update
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...and the generation field of 8W 20 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update These parts support Intel® Trusted Execution Technology (Intel® TXT) 6. These parts have ... register accessible through Boundary Scan. These processors support the 775_VR_CONFIG_06 specifications. 2. These parts support Intel® 64 Architecture 4. These parts support Execute Disable Bit Feature 7. These processors support the 775_VR_CONFIG_05B specifications 3. The following...
...and the generation field of 8W 20 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update These parts support Intel® Trusted Execution Technology (Intel® TXT) 6. These parts have ... register accessible through Boundary Scan. These processors support the 775_VR_CONFIG_06 specifications. 2. These parts support Intel® 64 Architecture 4. These parts support Execute Disable Bit Feature 7. These processors support the 775_VR_CONFIG_05B specifications 3. The following...
Specification Update
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... contain a workaround for this erratum, a logical processor may not resume execution until the next targeted interrupt event or O/S timer tick following a locked store that spans across cache lines. REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 Problem: REP CMPS ...(Compare String) and SCAS (Scan String) instructions in 64-bit mode may be observed and RFLAGS may terminate before the count in RCX reaches...
... contain a workaround for this erratum, a logical processor may not resume execution until the next targeted interrupt event or O/S timer tick following a locked store that spans across cache lines. REP CMPS/SCAS Operations May Terminate Early in 64-bit Mode when RCX >= 0X100000000 Problem: REP CMPS ...(Compare String) and SCAS (Scan String) instructions in 64-bit mode may be observed and RFLAGS may terminate before the count in RCX reaches...
Specification Update
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...image if all of the following conditions are true: • The processor is in 64-bit mode. • The last floating point operation was in the EFLAGS register and/or the AM bit (bit 18) of the FPU Data (Operand) Pointer may behave unpredictably. ... and dependent upon ongoing store operations may livelock. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 37 Specification Update Workaround: Clear the AC flag (bit 18) in compatibility mode • Bit 31 of Changes. Workaround: It is possible for...
...image if all of the following conditions are true: • The processor is in 64-bit mode. • The last floating point operation was in the EFLAGS register and/or the AM bit (bit 18) of the FPU Data (Operand) Pointer may behave unpredictably. ... and dependent upon ongoing store operations may livelock. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 37 Specification Update Workaround: Clear the AC flag (bit 18) in compatibility mode • Bit 31 of Changes. Workaround: It is possible for...
Specification Update
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... than or equal to 248. Errata AI58. AI59. AI60. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 43 Specification Update Status: For the steppings affected, see the Summary Tables of -Order Stores For String Operations in 64-bit Mode with Count Greater or Equal to 248 May Terminate...
... than or equal to 248. Errata AI58. AI59. AI60. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 43 Specification Update Status: For the steppings affected, see the Summary Tables of -Order Stores For String Operations in 64-bit Mode with Count Greater or Equal to 248 May Terminate...
Specification Update
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...Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 45 Specification Update Status: For the steppings affected, see the Summary Tables of software applications. Implication: LBR, BTS and BTM may ensure that no processor is currently accessing a page that is scheduled to all 1's. Returning to Real Mode from SMM with bits...has not yet completed. LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should not change the value of the instruction, since this behavior in...
...Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 45 Specification Update Status: For the steppings affected, see the Summary Tables of software applications. Implication: LBR, BTS and BTM may ensure that no processor is currently accessing a page that is scheduled to all 1's. Returning to Real Mode from SMM with bits...has not yet completed. LBR, BTS, BTM May Report a Wrong Address when an Exception/Interrupt Occurs in 64-bit Mode Problem: An exception/interrupt event should not change the value of the instruction, since this behavior in...
Specification Update
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... Cleared After Code Breakpoint Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following conditions occur: • The processor is running in VMX non-root as a 64 bit mode guest; • The "CR8-load...happens: 1) POP instruction to CR8 Instruction In a system supporting Intel® Virtualization Technology, the BS bit (bit 14 of BTM/BTS branch-from Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 49 Specification Update When BTM (Branch ...
... Cleared After Code Breakpoint Problem: B0-B3 bits (breakpoint conditions detect flags, bits [3:0]) in DR6 may not be properly cleared when the following conditions occur: • The processor is running in VMX non-root as a 64 bit mode guest; • The "CR8-load...happens: 1) POP instruction to CR8 Instruction In a system supporting Intel® Virtualization Technology, the BS bit (bit 14 of BTM/BTS branch-from Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 49 Specification Update When BTM (Branch ...
Specification Update
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...; Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 51 Specification Update Workaround: Do not use TPR shadow" VM-execution control is accessed by another thread performs cacheable write to the Intel® 64 and IA-32 Architectures Software Developer's Manual,...by Two Subsequent Loads Problem: When data of Store to this erratum with a 16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and leave bits 63:16 at the destination register unmodified, instead of the Destination Register Unmodified Problem:...
...; Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 51 Specification Update Workaround: Do not use TPR shadow" VM-execution control is accessed by another thread performs cacheable write to the Intel® 64 and IA-32 Architectures Software Developer's Manual,...by Two Subsequent Loads Problem: When data of Store to this erratum with a 16 bit operand size (REX.W =0 and 66H prefix) will only store 16 bits and leave bits 63:16 at the destination register unmodified, instead of the Destination Register Unmodified Problem:...
Specification Update
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... the code segment limit. Update of Attribute Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Problem: Updating a page directory entry... to Multiple Processors" In volume 3A of the Intel® 64 and IA-32 Architecture Software Developer's Manual), in conjunction with a complex sequence of internal processor micro-architectural events...still be asserted. 54 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI92. Intel has not observed this ...
... the code segment limit. Update of Attribute Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Problem: Updating a page directory entry... to Multiple Processors" In volume 3A of the Intel® 64 and IA-32 Architecture Software Developer's Manual), in conjunction with a complex sequence of internal processor micro-architectural events...still be asserted. 54 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI92. Intel has not observed this ...
Specification Update
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...instructions, while the counter is configured for the target linear address has an A (Accessed) bit that is modified without TLB Invalidation May Result in Improper Handling of Code #PF Code #PF...Combining) buffers in the same way as UC (Uncacheable) memory type stores do. Due to Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A "Methods of Changes. Workaround: None identified...(Page Directory Entry) is clear 56 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
...instructions, while the counter is configured for the target linear address has an A (Accessed) bit that is modified without TLB Invalidation May Result in Improper Handling of Code #PF Code #PF...Combining) buffers in the same way as UC (Uncacheable) memory type stores do. Due to Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A "Methods of Changes. Workaround: None identified...(Page Directory Entry) is clear 56 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
Specification Update
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...bit 0 (blocking by STI) and bit 1 (blocking by the TPR Shadow", in this erratum; This may cause the processor to perform incorrect operations leading to the TPR shadow. Workaround: VMM software raising the value of Changes. 64 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor...the TPR-threshold VMexecution control field. Workaround: None identified. Intel has not observed this erratum with any VM entry performed with the "use of the VMCS (bit 0 - Intel does not support the use TPR shadow", "activate secondary ...
...bit 0 (blocking by STI) and bit 1 (blocking by the TPR Shadow", in this erratum; This may cause the processor to perform incorrect operations leading to the TPR shadow. Workaround: VMM software raising the value of Changes. 64 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor...the TPR-threshold VMexecution control field. Workaround: None identified. Intel has not observed this erratum with any VM entry performed with the "use of the VMCS (bit 0 - Intel does not support the use TPR shadow", "activate secondary ...
Specification Update
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... the "virtual NMIs" VM-execution control set to 1, this erratum. AI126. Intel has not observed this erratum, only 66 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI125. Implication: VM-entry failures that cause ...triggered by a complex sequence of internal processor micro-architectural events, may not reflect the correct state of the enable bit in the IA32_MC1_CTL MSR at the time of blocking by a VM-Entry Failure The Intel® 64 and IA-32 Architectures Software Developer's Manual...
... the "virtual NMIs" VM-execution control set to 1, this erratum. AI126. Intel has not observed this erratum, only 66 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI125. Implication: VM-entry failures that cause ...triggered by a complex sequence of internal processor micro-architectural events, may not reflect the correct state of the enable bit in the IA32_MC1_CTL MSR at the time of blocking by a VM-Entry Failure The Intel® 64 and IA-32 Architectures Software Developer's Manual...
Specification Update
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...time of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide. Workaround: VMM software should always set to 1 in the SMM VMCS to Exceptions" of the last SMM VM Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and... Abort was in the LMA bit (IA32_EFER.LMA.LMA[bit 10]) in effect and that follows the guidelines given in the section "Handling VM Exits Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS. Intel has not observed this erratum ...
...time of Intel® 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide. Workaround: VMM software should always set to 1 in the SMM VMCS to Exceptions" of the last SMM VM Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and... Abort was in the LMA bit (IA32_EFER.LMA.LMA[bit 10]) in effect and that follows the guidelines given in the section "Handling VM Exits Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS. Intel has not observed this erratum ...
Specification Update
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... may result in 64-bit mode, a register IP-relative instruction result may be 1 only if the "host address-space size" VM-exit control is 1 in the executive VMCS. Status: For the steppings affected, see the Summary Tables of Changes. § 68 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000...
... may result in 64-bit mode, a register IP-relative instruction result may be 1 only if the "host address-space size" VM-exit control is 1 in the executive VMCS. Status: For the steppings affected, see the Summary Tables of Changes. § 68 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000...