Data Sheet
Page 86
... halted; When one of the logical processors executes the HALT instruction, that the processor FSB frequency is in the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for details about the HALT and Enhanced HALT states. Enhanced HALT Powerdown State Enhanced HALT is... entered when all logical processors have executed the HALT or MWAIT instructions. Refer to the Stop Grant State. HALT and Enhanced HALT Powerdown States The Prescott processor supports the HALT or Enhanced HALT powerdown state.
... halted; When one of the logical processors executes the HALT instruction, that the processor FSB frequency is in the HALT Power Down state. See the Intel Architecture Software Developer's Manual, Volume III: System Programmer's Guide for details about the HALT and Enhanced HALT states. Enhanced HALT Powerdown State Enhanced HALT is... entered when all logical processors have executed the HALT or MWAIT instructions. Refer to the Stop Grant State. HALT and Enhanced HALT Powerdown States The Prescott processor supports the HALT or Enhanced HALT powerdown state.