Service Manual
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... Y10 ADC_I_NEG W10 ADC_I_POS W9 ADC_Q_NEG Y9 ADC_Q_POS Y8 DAC_I_NEG W8 DAC_I_POS W7 DAC_Q_NEG Y7 DAC_Q_POS AB7 TX_POW Copyright © 2007 LG Electronics. XGAM Subsystem The XGAM subsystem is a slave peripheral under control of operation within the digital baseband controller, as well ...reserved. Schematic of WCDMA RF Interface - 25 - Technical Brief E. The XGAM subsystem is responsible for clock generation and clock and reset distribution within the digital baseband controller. F. Individual blocks can also be graphics, still images, or video. The XGAM also provides support...
... Y10 ADC_I_NEG W10 ADC_I_POS W9 ADC_Q_NEG Y9 ADC_Q_POS Y8 DAC_I_NEG W8 DAC_I_POS W7 DAC_Q_NEG Y7 DAC_Q_POS AB7 TX_POW Copyright © 2007 LG Electronics. XGAM Subsystem The XGAM subsystem is a slave peripheral under control of operation within the digital baseband controller, as well ...reserved. Schematic of WCDMA RF Interface - 25 - Technical Brief E. The XGAM subsystem is responsible for clock generation and clock and reset distribution within the digital baseband controller. F. Individual blocks can also be graphics, still images, or video. The XGAM also provides support...
Service Manual
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SIMDAT0 SIMCLK0 SIMRST0 SIM (Interface between DBB and ABB) SIM card bidirectional data line SIM card reference clock SIM card async/sync reset Table 3-1-2. SIM Interface Asta SIMDAT0 SIMCLK0 SIMRST0 VDD E 10K SIMVCC Veronica SDAT SCLK SRST SIMDAT SIMCLK SIMRST 10K VDD DAT CLK CARD RST Figure 3-1-7. Inc. ...-1-6. SIMDAT0, SIMCLK0, SIMRST0 ports are used to communicate DBB(Asta) with ABB(Veronica) and filter. SIM Interface LGE Internal Use Only - 26 - Copyright © 2007 LG Electronics. 3.
SIMDAT0 SIMCLK0 SIMRST0 SIM (Interface between DBB and ABB) SIM card bidirectional data line SIM card reference clock SIM card async/sync reset Table 3-1-2. SIM Interface Asta SIMDAT0 SIMCLK0 SIMRST0 VDD E 10K SIMVCC Veronica SDAT SCLK SRST SIMDAT SIMCLK SIMRST 10K VDD DAT CLK CARD RST Figure 3-1-7. Inc. ...-1-6. SIMDAT0, SIMCLK0, SIMRST0 ports are used to communicate DBB(Asta) with ABB(Veronica) and filter. SIM Interface LGE Internal Use Only - 26 - Copyright © 2007 LG Electronics. 3.
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...from Veronica • Power - RESOUT2_n signal of Veronica • Reset - HCI interface between Asta/Veronica and STLC2590C • ANT - 2.4GHz, 50 ohm matching LGE Internal Use Only - 36 - Copyright © 2007 LG Electronics. Low power clock : 32.768kHz ➝ Supplied RTCCLK ...of Asta controls STLC2590C reset. • SPI - Audio signal interface between Asta and STLC2590C • PCM - All right reserved. Only for training and service purposes Clock request ➝ Connected to CLKREQ of STLC2590C • Clock - KU580 Bluetooth Schematic APP_GP04_FM_GPIO2 TP402 ...
...from Veronica • Power - RESOUT2_n signal of Veronica • Reset - HCI interface between Asta/Veronica and STLC2590C • ANT - 2.4GHz, 50 ohm matching LGE Internal Use Only - 36 - Copyright © 2007 LG Electronics. Low power clock : 32.768kHz ➝ Supplied RTCCLK ...of Asta controls STLC2590C reset. • SPI - Audio signal interface between Asta and STLC2590C • PCM - All right reserved. Only for training and service purposes Clock request ➝ Connected to CLKREQ of STLC2590C • Clock - KU580 Bluetooth Schematic APP_GP04_FM_GPIO2 TP402 ...
Service Manual
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3. Copyright © 2007 LG Electronics. Technical Brief 3.1.13 Power On Sequence ➀ User presses END key and then ONSWAn signal is changed to Asta. Veronica ➁ ➂ Power for Asta. ➃ Veronica releases the power reset signal(PWRRSTn) and generates an interrupt(IRQ0n) to Low. ➁ Veronica initiates the internal oscillator and powers...
3. Copyright © 2007 LG Electronics. Technical Brief 3.1.13 Power On Sequence ➀ User presses END key and then ONSWAn signal is changed to Asta. Veronica ➁ ➂ Power for Asta. ➃ Veronica releases the power reset signal(PWRRSTn) and generates an interrupt(IRQ0n) to Low. ➁ Veronica initiates the internal oscillator and powers...
Service Manual
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...all set-up to interface both frame buffer and temporary data. The programmable PDI block is 12 MByte/s. Copyright © 2007 LG Electronics. All right reserved. GAM Controller(GAMCON) The GAM Controller (GAMCON) is responsible for training and service purposes GAMCON also distributes the ...GAM reset signal to the display. The reset signals CIRES_N and PDIRES_N are three image areas with other two areas used to 16 MHz. Graphics RAM (GRAM) Block GAM...
...all set-up to interface both frame buffer and temporary data. The programmable PDI block is 12 MByte/s. Copyright © 2007 LG Electronics. All right reserved. GAM Controller(GAMCON) The GAM Controller (GAMCON) is responsible for training and service purposes GAMCON also distributes the ...GAM reset signal to the display. The reset signals CIRES_N and PDIRES_N are three image areas with other two areas used to 16 MHz. Graphics RAM (GRAM) Block GAM...
Service Manual
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... range of incoming images and potential errors. The I2C interface and GPIO are also different for training and service purposes - 43 - The camera module reset signal is YUV 4:2:2 (raw binary image data) according to the camera module, but only YUV data can also be in external memory. CDI allows... camera module to detect the end of other data types such as JPEG or RGB (as long as overflow conditions. Copyright © 2007 LG Electronics. There is nothing preventing the use of an image and perform some truncation as well as the timing is followed), but they pass ...
... range of incoming images and potential errors. The I2C interface and GPIO are also different for training and service purposes - 43 - The camera module reset signal is YUV 4:2:2 (raw binary image data) according to the camera module, but only YUV data can also be in external memory. CDI allows... camera module to detect the end of other data types such as JPEG or RGB (as long as overflow conditions. Copyright © 2007 LG Electronics. There is nothing preventing the use of an image and perform some truncation as well as the timing is followed), but they pass ...
Service Manual
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... 20-pin Board to Board through 70 pin Board to camera module and receive 32.2MHz pixel clock(15fps), vertical sync signal, horizontal sync signal, reset signal and 8bits YUV data from camera module. Vertical sync. GND I2C Data I2C Clock GND Table 3-2-1. 3. Its interface is controlled by I2C port. Pin... Only - 46 - Inc. The camera port supply 24MHz master clock to Board connector. Interface between VGA Camera Module and FPCB (in DB3100. Copyright © 2007 LG Electronics. Only for output RESET STANDBY GND 1.5V 2.8V 2.8V GND Master Input clock Hertical sync.
... 20-pin Board to Board through 70 pin Board to camera module and receive 32.2MHz pixel clock(15fps), vertical sync signal, horizontal sync signal, reset signal and 8bits YUV data from camera module. Vertical sync. GND I2C Data I2C Clock GND Table 3-2-1. 3. Its interface is controlled by I2C port. Pin... Only - 46 - Inc. The camera port supply 24MHz master clock to Board connector. Interface between VGA Camera Module and FPCB (in DB3100. Copyright © 2007 LG Electronics. Only for output RESET STANDBY GND 1.5V 2.8V 2.8V GND Master Input clock Hertical sync.
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Technical Brief 3.2.5 Display & LCD FPC Interface LCD module include device in DB3100. Signal 1 GND 2 LED C1 3 LED C4 4 LED A 5 GND 6 RESET 7 GND 8 D15 9 D13 10 D11 11 D9 12 D7 13 D5 14 D3 15 D1 16 RD/ 17 RS 18 VSYNC 19 IOVCC(1.8V) 20 ... 36 IF(IM) 37 GND 38 LED C3 39 LED C2 40 GND Table 3-2-4. Only for training and service purposes 3. No. Inc. Copyright © 2007 LG Electronics. The LCD is connected to Key PCB with 40-pin Connector in sub PCB. All right reserved. Device in LCD Module LCD Module is...
Technical Brief 3.2.5 Display & LCD FPC Interface LCD module include device in DB3100. Signal 1 GND 2 LED C1 3 LED C4 4 LED A 5 GND 6 RESET 7 GND 8 D15 9 D13 10 D11 11 D9 12 D7 13 D5 14 D3 15 D1 16 RD/ 17 RS 18 VSYNC 19 IOVCC(1.8V) 20 ... 36 IF(IM) 37 GND 38 LED C3 39 LED C2 40 GND Table 3-2-4. Only for training and service purposes 3. No. Inc. Copyright © 2007 LG Electronics. The LCD is connected to Key PCB with 40-pin Connector in sub PCB. All right reserved. Device in LCD Module LCD Module is...