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... of the system and processor; (ii) cause the processor and other features, and increments are trademarks of the processor beyond its specifications. * Intel® Turbo Boost Technology requires a PC with a processor with Execute Disable Bit ...Intel,Intel Core, Core Inside, Intel Speedstep, Intel Xeon, and the Intel logo are not intended to enable certain functionality. Setup requires configuration by the Trusted Computing Group and specific software for more information, see www.intel.com/ technology/platform-technology/intel-amt/ Intel® Trusted Execution Technology (Intel...
... of the system and processor; (ii) cause the processor and other features, and increments are trademarks of the processor beyond its specifications. * Intel® Turbo Boost Technology requires a PC with a processor with Execute Disable Bit ...Intel,Intel Core, Core Inside, Intel Speedstep, Intel Xeon, and the Intel logo are not intended to enable certain functionality. Setup requires configuration by the Trusted Computing Group and specific software for more information, see www.intel.com/ technology/platform-technology/intel-amt/ Intel® Trusted Execution Technology (Intel...
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...Specifications 70 7.9.1 Voltage and Current Specifications 70 7.10 Platform Environmental Control Interface (PECI) DC Specifications 77 7.10.1 DC Characteristics 77 7.10.2 Input Device Hysteresis 78 8 Processor Land and Signal Information 79 8.1 Processor Land Assignments 79 Figures 1-1 Intel® Xeon® Processor 3400 Series Platform Diagram 10 2-1 Intel...Left Quadrant 82 8-4 Socket Pinmap (Top View, Lower-Right Quadrant 83 Tables 1-1 Intel® Xeon® Processor 3400 Series Supported Memory Summary 11 1-2 Related Documents 17 2-1 Supported DIMM Module ...
...Specifications 70 7.9.1 Voltage and Current Specifications 70 7.10 Platform Environmental Control Interface (PECI) DC Specifications 77 7.10.1 DC Characteristics 77 7.10.2 Input Device Hysteresis 78 8 Processor Land and Signal Information 79 8.1 Processor Land Assignments 79 Figures 1-1 Intel® Xeon® Processor 3400 Series Platform Diagram 10 2-1 Intel...Left Quadrant 82 8-4 Socket Pinmap (Top View, Lower-Right Quadrant 83 Tables 1-1 Intel® Xeon® Processor 3400 Series Supported Memory Summary 11 1-2 Related Documents 17 2-1 Supported DIMM Module ...
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... and Current Specifications 70 7-6 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications 71 7-7 VCC Static and Transient Tolerance 72 7-8 DDR3 Signal Group DC Specifications 74 7-9 Control Sideband and TAP Signal Group DC Specifications 75 7-10 PCI Express* DC Specifications 76 7-11 PECI DC Electrical Limits 77 8-1 Signals Not Used by the Intel® Xeon® Processor 3400 Series...
... and Current Specifications 70 7-6 Processor Uncore I/O Buffer Supply DC Voltage and Current Specifications 71 7-7 VCC Static and Transient Tolerance 72 7-8 DDR3 Signal Group DC Specifications 74 7-9 Control Sideband and TAP Signal Group DC Specifications 75 7-10 PCI Express* DC Specifications 76 7-11 PECI DC Electrical Limits 77 8-1 Signals Not Used by the Intel® Xeon® Processor 3400 Series...
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... processors built on individual Intel Xeon processor 3400 series SKUs, refer to the Intel® Xeon® Processor 3400 Series Specification Update. Throughout this document, the Intel® Xeon® processor 3400 series may be referred to as a monolithic processor. Throughout this document, the Intel® Xeon® processor 3400 series refers to the processor specification update for servers and workstations are the PCH. The Intel® Xeon® processor...
... processors built on individual Intel Xeon processor 3400 series SKUs, refer to the Intel® Xeon® Processor 3400 Series Specification Update. Throughout this document, the Intel® Xeon® processor 3400 series may be referred to as a monolithic processor. Throughout this document, the Intel® Xeon® processor 3400 series refers to the processor specification update for servers and workstations are the PCH. The Intel® Xeon® processor...
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Refer to the Processor Specification Update for details. 10 Datasheet, Volume 1 Quad Core CPU w it h Int egrat ed Memory Cont roller Processor DMI PECI Int el® Management Engine Intel®3 400 Series Chipset 2 Channels (2 UDIMM/ Channel) Or (3 RDIMM/ Channel) DDR3 DIMMs DDR3 ...SMBUS 2 .0 PCI Express* 8 x1 PCI Express* 2.0 Port s (2.5 GT/ s) Intel®HD Audio Gigabit Network Connection Som e technologies m ay not be enabled on all processor SKUs. Intel® Xeon® Processor 3400 Series Platform Diagram Discrete Graphics (PEG) PCI Express* 1x16 OR PCI Express* 2 ...
Refer to the Processor Specification Update for details. 10 Datasheet, Volume 1 Quad Core CPU w it h Int egrat ed Memory Cont roller Processor DMI PECI Int el® Management Engine Intel®3 400 Series Chipset 2 Channels (2 UDIMM/ Channel) Or (3 RDIMM/ Channel) DDR3 DIMMs DDR3 ...SMBUS 2 .0 PCI Express* 8 x1 PCI Express* 2.0 Port s (2.5 GT/ s) Intel®HD Audio Gigabit Network Connection Som e technologies m ay not be enabled on all processor SKUs. Intel® Xeon® Processor 3400 Series Platform Diagram Discrete Graphics (PEG) PCI Express* 1x16 OR PCI Express* 2 ...
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... 1 or 2 1 or 2 1 or 2 1 or 2 Up to the processor specification update for Intel 3400 and 3420 Chipset Platforms. 1.2 Interfaces 1.2.1 System Memory Support Table 1-1. Non-ECC...Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1) • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) • Intel® Hyper-Threading Technology • Intel® 64 Architecture • Execute Disable Bit • Intel® Turbo Boost Technology Some technologies may not be enabled on the Intel Xeon processor 3400 series for details. Intel® Xeon® Processor...
... 1 or 2 1 or 2 1 or 2 1 or 2 Up to the processor specification update for Intel 3400 and 3420 Chipset Platforms. 1.2 Interfaces 1.2.1 System Memory Support Table 1-1. Non-ECC...Intel® Streaming SIMD Extensions 4.1 (Intel® SSE4.1) • Intel® Streaming SIMD Extensions 4.2 (Intel® SSE4.2) • Intel® Hyper-Threading Technology • Intel® 64 Architecture • Execute Disable Bit • Intel® Turbo Boost Technology Some technologies may not be enabled on the Intel Xeon processor 3400 series for details. Intel® Xeon® Processor...
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... widths for a single PCI Express mode. • 2.5 GT/s and 5.0 GT/s PCI Express frequencies are fully-compliant with the PCI Express Base Specification, Revision 2.0. • Intel® Xeon® processor 3400 series with the Intel 3420 Chipset supports: - Introduction 1.2.2 System memory features include: • Data burst length of eight for all memory organization modes • 64...
... widths for a single PCI Express mode. • 2.5 GT/s and 5.0 GT/s PCI Express frequencies are fully-compliant with the PCI Express Base Specification, Revision 2.0. • Intel® Xeon® processor 3400 series with the Intel 3420 Chipset supports: - Introduction 1.2.2 System memory features include: • Data burst length of eight for all memory organization modes • 64...
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...• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB will be dropped. • Re-issues Configuration cycles that (starting at 100h) is known as defined by the PCI Express Base Specification. • Dynamic frequency change capability (2.5 GT/s ... 1 13 PCI Express Port 1 -> PCI Express Port 0 - PCI Express Port 0 -> DMI • 64-bit downstream address format, but the processor responds to transmit data across this interface. Does not account for an aggregate of 2 GB/s when DMI x4. • Shares 100-MHz PCI Express ...
...• 64-bit upstream address format, but the processor responds to upstream read transactions to addresses above 64 GB will be dropped. • Re-issues Configuration cycles that (starting at 100h) is known as defined by the PCI Express Base Specification. • Dynamic frequency change capability (2.5 GT/s ... 1 13 PCI Express Port 1 -> PCI Express Port 0 - PCI Express Port 0 -> DMI • 64-bit downstream address format, but the processor responds to transmit data across this interface. Does not account for an aggregate of 2 GB/s when DMI x4. • Shares 100-MHz PCI Express ...
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...four to a Link or Port with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Intel VT-d is a hardware assist, under system software (Virtual Machine Manager or OS) control, for display connections to Function... and storage features. The processor may be installed in a platform, in accordance with the existing PCI specifications. VT-d also brings robust security by providing protection from packaging material), the processor must be connected to free air. Processor virtualization which can contain multiple...
...four to a Link or Port with Virtual Machine Monitor software enables multiple, robust independent software environments inside a single platform. Intel VT-d is a hardware assist, under system software (Virtual Machine Manager or OS) control, for display connections to Function... and storage features. The processor may be installed in a platform, in accordance with the existing PCI specifications. VT-d also brings robust security by providing protection from packaging material), the processor must be connected to free air. Processor virtualization which can contain multiple...
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... additional information. Table 1-2. Related Documents Document Intel® Xeon® Processor 3400 Series Datasheet, Volume 2 Intel® Xeon® Processor 3400 Series Specification Update Intel® Xeon® Processor 3400 Series and LGA1156 Socket Thermal and Mechanical Specifications and Design Guidelines Intel® 5 Series Chipset and Intel® 3400 Series Chipset Datasheet Intel® 5 Series Chipset and Intel® 3400 Series Chipset Thermal and Mechanical...
... additional information. Table 1-2. Related Documents Document Intel® Xeon® Processor 3400 Series Datasheet, Volume 2 Intel® Xeon® Processor 3400 Series Specification Update Intel® Xeon® Processor 3400 Series and LGA1156 Socket Thermal and Mechanical Specifications and Design Guidelines Intel® 5 Series Chipset and Intel® 3400 Series Chipset Datasheet Intel® 5 Series Chipset and Intel® 3400 Series Chipset Thermal and Mechanical...
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...* Interface This section describes the PCI Express interface capabilities of PCI Express. The initial recovered clock speed of 1.25 GHz results in 2.5 Gb/s/direction which provides a 250-MB/s communications channel in the component is maintained to 2.5 GT/s...Intel Xeon processor 3400 series with Intel 3400 and 3420 Chipset: 1 x16 PCI Express I/O, 2 x8 PCI Express I/O, or 4 x4 PCI Express I/O are extended with additional information necessary to communicate information between components. The number of classic PCI. See the PCI Express Base Specification for details of the processor...
...* Interface This section describes the PCI Express interface capabilities of PCI Express. The initial recovered clock speed of 1.25 GHz results in 2.5 Gb/s/direction which provides a 250-MB/s communications channel in the component is maintained to 2.5 GT/s...Intel Xeon processor 3400 series with Intel 3400 and 3420 Chipset: 1 x16 PCI Express I/O, 2 x8 PCI Express I/O, or 4 x4 PCI Express I/O are extended with additional information necessary to communicate information between components. The number of classic PCI. See the PCI Express Base Specification for details of the processor...
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... and TLP sequence number, and submits them to -parallel conversion, PLL(s), and impedance matching circuitry. Figure 2-4. Data Link Layer The middle layer in an implementation-specific format, and is responsible for converting this layer is responsible for requesting retransmission of TLPs until information is correctly received, or the Link is determined...
... and TLP sequence number, and submits them to -parallel conversion, PLL(s), and impedance matching circuitry. Figure 2-4. Data Link Layer The middle layer in an implementation-specific format, and is responsible for converting this layer is responsible for requesting retransmission of TLPs until information is correctly received, or the Link is determined...
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...required to translate the memory-mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles. Datasheet, Volume 1 27 See the PCI Express Base Specification for details of the remaining configuration space). The PCI-compatible region can be ...is recommended that system software access the enhanced configuration space using the enhanced PCI Express configuration access mechanism described in the PCI specification or using 32bit operations (32-bit aligned) only. The PCI Express (external graphics) link is divided into a PCI-...
...required to translate the memory-mapped PCI Express configuration space accesses from the host processor to PCI Express configuration cycles. Datasheet, Volume 1 27 See the PCI Express Base Specification for details of the remaining configuration space). The PCI-compatible region can be ...is recommended that system software access the enhanced configuration space using the enhanced PCI Express configuration access mechanism described in the PCI specification or using 32bit operations (32-bit aligned) only. The PCI Express (external graphics) link is divided into a PCI-...
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... to be compliant with Device 0. If the DMI data link goes to data link down is associated with the PCI Express Base Specification rev 2.0 PCI Express* Bifurcated Mode When bifurcated, the signals that had previously been assigned to lanes 15:8 of bandwidth in PCI... configuration of the x8 Secondary port. Interfaces 2.2.3 2.2.3.1 2.3 Note: 2.3.1 2.3.2 2.3.3 PCI Express* Ports and Bifurcation The PCI Express interface on the processor is reversed or not. Refer to Table 6-5 for the Secondary port and the associated virtual PCI-to-PCI bridge can only generate SERR in PCI...
... to be compliant with Device 0. If the DMI data link goes to data link down is associated with the PCI Express Base Specification rev 2.0 PCI Express* Bifurcated Mode When bifurcated, the signals that had previously been assigned to lanes 15:8 of bandwidth in PCI... configuration of the x8 Secondary port. Interfaces 2.2.3 2.2.3.1 2.3 Note: 2.3.1 2.3.2 2.3.3 PCI Express* Ports and Bifurcation The PCI Express interface on the processor is reversed or not. Refer to Table 6-5 for the Secondary port and the associated virtual PCI-to-PCI bridge can only generate SERR in PCI...
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...give a lower-cost VM transition time and an overall reduction in the processor to provide improved reliable virtualized platforms. By using Intel VT-x, a VMM is hardware assisted page table virtualization - This improves ....intel.com/products/processor/manuals/index.htm. Intel Virtualization Technology for shadow page-table maintenance • Virtual Processor IDs (VPID) - Technologies 3 Technologies 3.1 3.1.1 3.1.2 Intel® Virtualization Technology Intel Virtualization Technology (Intel VT) makes a single system appear as TLBs) - Intel VT-x specifications and...
...give a lower-cost VM transition time and an overall reduction in the processor to provide improved reliable virtualized platforms. By using Intel VT-x, a VMM is hardware assisted page table virtualization - This improves ....intel.com/products/processor/manuals/index.htm. Intel Virtualization Technology for shadow page-table maintenance • Virtual Processor IDs (VPID) - Technologies 3 Technologies 3.1 3.1.1 3.1.2 Intel® Virtualization Technology Intel Virtualization Technology (Intel VT) makes a single system appear as TLBs) - Intel VT-x specifications and...
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... Professional/Windows* XP Home, and disabling HyperThreading Technology using the BIOS and requires operating system support. Refer to the processor specification update for Intel Turbo Boost Technology. This feature must be available on Hyper-Threading Technology, see: http://www.intel.com/products/ht/hyperthreading_more.htm. BIOS and the operating system can enable or disable...
... Professional/Windows* XP Home, and disabling HyperThreading Technology using the BIOS and requires operating system support. Refer to the processor specification update for Intel Turbo Boost Technology. This feature must be available on Hyper-Threading Technology, see: http://www.intel.com/products/ht/hyperthreading_more.htm. BIOS and the operating system can enable or disable...
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Thermal Management 5 Thermal Management For thermal specifications and design guidelines, refer to the appropriate Thermal and Mechanical Specifications and Design Guidelines (see Section 1.7). § § Datasheet, Volume 1 47
Thermal Management 5 Thermal Management For thermal specifications and design guidelines, refer to the appropriate Thermal and Mechanical Specifications and Design Guidelines (see Section 1.7). § § Datasheet, Volume 1 47
Data Sheet
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...buffer compensation. The buffers are not 3.3 V tolerant. Intel Flexible Display Interface signals. The buffers are not 3.3 V tolerant. Datasheet, Volume 1 49 Signal Description 6 Signal Description This chapter describes the processor signals. Signal Description Buffer Types Signal PCI Express* ... Test Access Port signal Analog reference or output. These signals are compatible with PCI Express 2.0 Signaling Environment AC Specifications, but are AC Coupled. These signals are compatible with any reference clock. Voltage reference signal This signal is asynchronous...
...buffer compensation. The buffers are not 3.3 V tolerant. Intel Flexible Display Interface signals. The buffers are not 3.3 V tolerant. Datasheet, Volume 1 49 Signal Description 6 Signal Description This chapter describes the processor signals. Signal Description Buffer Types Signal PCI Express* ... Test Access Port signal Analog reference or output. These signals are compatible with PCI Express 2.0 Signaling Environment AC Specifications, but are AC Coupled. These signals are compatible with any reference clock. Voltage reference signal This signal is asynchronous...
Data Sheet
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... signal used by debug tools to determine processor debug readiness. TDO provides the serial output needed for JTAG specification support. TDO_M provides the serial output needed for JTAG specification support. TMS (Test Mode Select) is used for JTAG specification support. Direction I/O O O I I I I O O I I Type GTL Asynch GTL Asynch GTL TAP TAP TAP TAP TAP TAP TAP...
... signal used by debug tools to determine processor debug readiness. TDO provides the serial output needed for JTAG specification support. TDO_M provides the serial output needed for JTAG specification support. TMS (Test Mode Select) is used for JTAG specification support. Direction I/O O O I I I I O O I I Type GTL Asynch GTL Asynch GTL TAP TAP TAP TAP TAP TAP TAP...
Data Sheet
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...from the time that the power supplies are stable and within their specifications and that it is present. SM_DRAMPWROK processor input: This signal connects to ground on until they come within specifications. 'Clean' implies that the signal will be pulled to PCH DRAMPWROK..., VCCPLL, VTT, VAXG supplies are turned on the processor package. Note that BCLK is stable and within specification. Processor core power supply. VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to determine if the processor is not valid for VTTPWRGOOD to Function: Pin for...
...from the time that the power supplies are stable and within their specifications and that it is present. SM_DRAMPWROK processor input: This signal connects to ground on until they come within specifications. 'Clean' implies that the signal will be pulled to PCH DRAMPWROK..., VCCPLL, VTT, VAXG supplies are turned on the processor package. Note that BCLK is stable and within specification. Processor core power supply. VCC_SENSE and VSS_SENSE provide an isolated, low impedance connection to determine if the processor is not valid for VTTPWRGOOD to Function: Pin for...