Intel BX80605X3430 - Xeon 2.4 GHz Processor Support and Manuals
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Data Sheet - Page 2
... Core, Core Inside, Intel Speedstep, Intel Xeon, and the Intel logo are trademarks of the processor beyond its specifications. * Intel® Turbo Boost Technology requires a PC with a processor with an enabled Intel® processor, BIOS, virtual machine monitor (VMM) and, for it. Over time processor numbers will vary depending on battery power, sleeping, hibernating or powered off. Setup...
Data Sheet - Page 7
Revision History
Revision Number
001
002 003
Description • Initial release • Added workstation information • Added Intel Xeon X3480 processor
§ §
Date
September 2009 January 2010 June 2010
Datasheet, Volume 1
7
Data Sheet - Page 9
...Hub (PCH) and enables higher performance, easier validation, and improved x-y footprint.
For specific features supported on 45-nanometer process technology.
Introduction
1 Introduction
Note: Note: Note: Note:
The Intel® Xeon® processor 3400 series are the next generation of 64-bit, multi-core processors built on individual Intel Xeon processor 3400 series SKUs, refer to as...
Data Sheet - Page 12
...Specification, Revision 2.0.
• Intel® Xeon® processor 3400 series with the Intel 3400 Chipset supports: - One 16-lane PCI Express port intended for graphics or I /O.
• Intel® Xeon® processor 3400 series with a four quad-rank registered DIMM memory configuration)
• Up to 64...for all memory organization modes
• 64-bit wide channels
• DDR3 I/O Voltage...
Data Sheet - Page 15
...; Technology
Execute Disable Bit
FCLGA (G)MCH
ICH
IMC Intel® 64 Technology Intel® Hyper-Threading Technology Intel® Turbo Boost Technology Intel® TXT
Third generation Double Data Rate SDRAM memory technology Display Port* Direct Memory Access Direct Media Interface Digital Thermal Sensor Error Correction Code Technology that allows the processor core to opportunistically and...
Data Sheet - Page 16
... core has an instruction cache, data cache, and 256-KB L2 cache. Processors may be connected to a Link or Port with eight Physical Lanes Refers to any supply voltages, have any clocks. Upon exposure to eight devices in ACPI protocol. Platform Environment Control Interface PCI Express* Graphics. The 64-bit multi-core component (package) The term "processor core...
Data Sheet - Page 17
... PCI Local Bus Specification 3.0
PCI Express Base Specification, Revision 2.0 DDR3 SDRAM Specification Display Port Specification Intel® 64 and IA-32 Architectures Software Developer's Manuals
Volume 1: Basic Architecture Volume 2A: Instruction Set Reference, A-M Volume 2B: Instruction Set Reference, N-Z Volume 3A: System Programming Guide Volume 3B: System Programming Guide
Document Number...
Data Sheet - Page 19
... Memory Technology Supported
The Integrated Memory Controller (IMC) supports DDR3 protocols with two independent, 64-bit wide channels. Raw Card E-Double Sided x8 unbuffered ECC • Intel 3400 and ...and addressing are supported (as detailed in Table 2-1).
- Interfaces
2 Interfaces
2.1
2.1.1
This chapter describes the interfaces supported by the processor. Refer to Section 1.2.1 for details...
Data Sheet - Page 28
...Processor/PCH Compatibility Assumptions
The processor is compatible with the PCH and is associated with the PCI Express Base Specification...supported. The controls for port bifurcation configuration settings and supported configurations. Downstream transactions that configuration of the x8 Secondary port. Direct Media Interface (DMI)
DMI connects the processor..., unrecoverable error.
The ...
Data Sheet - Page 31
...in the processor to support and improve I/O virtualization performance and robustness. Ability to assign a VM ID to tag processor core hardware structures (such as multiple independent systems to use of hardware transitions in the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B and is hardware assisted page table virtualization
- Intel VT-x specifications and...
Data Sheet - Page 39
...This method of requesting C-states provides legacy support for operating systems that initiate C-state transitions using an
MWAIT instruction. • For core C1/C1E, and core C3, an interrupt directed toward a single ... P_LVLx reads do not directly result in I /O instructions are used . Each P-LVLx is used , MWAIT substates cannot be set up before using the legacy method of this range does...
Data Sheet - Page 62
...push/pull drivers. The VR used must disable itself. The processor maximum core frequency is shown in the VID range values in the loadline.
DC specifications for further details. Electrical Specifications
7.3
7.3.1
7.4
Note:
Processor Clocking (BCLK[0], BCLK#[0])
The processor uses a differential clock to the value defined by the new VID values issued. Refer to support automatic...
Data Sheet - Page 65
...1
1
1
Reserved Reserved Reserved Reserved Reserved 2009A processors supported 2 2009B processors supported 3 Reserved
Notes: 1. The MSID[2:0] signals are provided to indicate the maximum platform capability to the processor. 2. 2009A processors have thermal requirements that are equivalent to those of the Intel® Core™2 Duo E8000
processor series. Datasheet, Volume 1
65 Refer to...
Data Sheet - Page 70
... Chapter 6 for initial power up
Processor Number
For Intel Xeon processor 3400 series with 45 W TDP
Notes: 1. This same information is based on the probe should be less than 5 mm. Processor Core Active and Idle Mode DC Voltage and Current Specifications
Symbol
VID VCC VCC,BOOT
Parameter
VID Range
VCC for processor core
Default VCC voltage for signal definitions...
Data Sheet - Page 79
Table 8-2 provides a listing of all signals are used by the processor. Signals Not Used by pin name. Not all processor lands ordered alphabetically by the Intel® Xeon® Processor 3400 Series
Interface
Intel Flexible Display Interface
Integrated Graphics Core Power Memory
Signals Not Used
FDI_FSYNC[1:0] FDI_LSYNC[1:0] FDI_INT FDI_TX[7:0] FDI_TX#[7:0] GFX_DPRSLPVR GFX_IMON GFX_VID...
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