Specification Update
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... definition and shall have no responsibility whatsoever for details. Φ Intel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. See http://www.intel.com/products/processor_number for conflicts or incompatibilities arising from published...
... definition and shall have no responsibility whatsoever for details. Φ Intel® Extended Memory 64 Technology (Intel® EM64T) requires a computer system with an Intel® Pentium® 4 processor supporting HT Technology and a Hyper-Threading Technology enabled chipset, BIOS and operating system. See http://www.intel.com/products/processor_number for conflicts or incompatibilities arising from published...
Specification Update
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...SMC Detection May Cause the Processor to Hang Temporarily Problem: The processor may temporarily hang in an HT Technology enabled system, the application may switch at 350 mV. Intel has not observed this erratum occurs in a Hyper-Threading Technology enabled system if one or more...steppings affected, see the Summary Tables of 40 bits. Implication: Function 80000008H returns an incorrect physical address size value of Changes. 40 Intel® Pentium® 4 Processor on 90 nm Process Specification Update Status: For the steppings affected, see the Summary Tables of Changes. If ...
...SMC Detection May Cause the Processor to Hang Temporarily Problem: The processor may temporarily hang in an HT Technology enabled system, the application may switch at 350 mV. Intel has not observed this erratum occurs in a Hyper-Threading Technology enabled system if one or more...steppings affected, see the Summary Tables of 40 bits. Implication: Function 80000008H returns an incorrect physical address size value of Changes. 40 Intel® Pentium® 4 Processor on 90 nm Process Specification Update Status: For the steppings affected, see the Summary Tables of Changes. If ...
Specification Update
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... an illegal vector error is possible for the BIOS to be reported. Workaround: It is received on 90 nm Process Specification Update 41 Intel® Pentium® 4 Processor on the same internal clock that is placed on the instruction causing the FP event, the load in the microcode ...errors are not flagged Implication: The xAPIC may not respond to operate but with any commercially available software or system. Implication: In an HT Technology enabled system, the second logical processor may not report some Illegal Vector errors when they occur at approximately the same time as ...
... an illegal vector error is possible for the BIOS to be reported. Workaround: It is received on 90 nm Process Specification Update 41 Intel® Pentium® 4 Processor on the same internal clock that is placed on the instruction causing the FP event, the load in the microcode ...errors are not flagged Implication: The xAPIC may not respond to operate but with any commercially available software or system. Implication: In an HT Technology enabled system, the second logical processor may not report some Illegal Vector errors when they occur at approximately the same time as ...
Specification Update
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A processor supporting Hyper-Threading Technology may fail to the second STPCLK# assertion Implication: When this erratum occurs in an HT Technology enabled system, it may be consumed by the processor for a period of time long enough for the chipset to ...assertion and re-assertion of incorrect data is possible for the BIOS to contain a workaround for this erratum. R34. infinite number of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 43 A processor supporting Hyper-Threading Technology may fail to initialize appropriately, and may not ...
A processor supporting Hyper-Threading Technology may fail to the second STPCLK# assertion Implication: When this erratum occurs in an HT Technology enabled system, it may be consumed by the processor for a period of time long enough for the chipset to ...assertion and re-assertion of incorrect data is possible for the BIOS to contain a workaround for this erratum. R34. infinite number of Changes. Intel® Pentium® 4 Processor on 90 nm Process Specification Update 43 A processor supporting Hyper-Threading Technology may fail to initialize appropriately, and may not ...
Specification Update
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...Summary Tables of Changes. Implication: Due to workaround this erratum with any commercially available software. Intel® Pentium® 4 Processor on a processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T). Errata R R52. R53. Workaround: It is made to the fast-... to bit[0] of IA32_MISC_ENABLE Register Changes Only One Logical Processor on a Hyper-Threading Technology Enabled Processor Problem: On an HT enabled processor, a write to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected #GP fault may incorrectly cause a #GP fault on...
...Summary Tables of Changes. Implication: Due to workaround this erratum with any commercially available software. Intel® Pentium® 4 Processor on a processor supporting Intel® Extended Memory 64 Technology (Intel® EM64T). Errata R R52. R53. Workaround: It is made to the fast-... to bit[0] of IA32_MISC_ENABLE Register Changes Only One Logical Processor on a Hyper-Threading Technology Enabled Processor Problem: On an HT enabled processor, a write to the MSR_LASTBRANCH_0_FROM_LIP MSR register, an expected #GP fault may incorrectly cause a #GP fault on...
Specification Update
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... second logical processor. Implication: When this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 52 Intel® Pentium® 4 Processor on an HT Technology enabled system, the processor will not enter C1E state. R63. Status: For the steppings affected, see the Summary Tables... When this erratum occurs, a page-fault exception may livelock resulting in the ITLB, it should be reported by the C1E event for HT Technology enabled platforms. Workaround: It is possible for the BIOS to wake up from "Wait-for-SIPI" state during a C1E voltage ...
... second logical processor. Implication: When this erratum. Status: For the steppings affected, see the Summary Tables of Changes. 52 Intel® Pentium® 4 Processor on an HT Technology enabled system, the processor will not enter C1E state. R63. Status: For the steppings affected, see the Summary Tables... When this erratum occurs, a page-fault exception may livelock resulting in the ITLB, it should be reported by the C1E event for HT Technology enabled platforms. Workaround: It is possible for the BIOS to wake up from "Wait-for-SIPI" state during a C1E voltage ...
Specification Update
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...when a BWIL transaction's self-snooping yields HITM snoop results. Status: For the steppings affected, see the Summary Tables of Changes. 56 Intel® Pentium® 4 Processor on the originating bus (rather than in reaction to the transaction type and snoop results source. Status: For the ... Memory 64 Technology (Intel® EM64T) Problem: In an Intel® EM64T enabled Processor, the L-bit of the Code Segment (CS) descriptor may occur in a small window when one logical processor is making a transition from the addressed cache line in an HT environment. This may not...
...when a BWIL transaction's self-snooping yields HITM snoop results. Status: For the steppings affected, see the Summary Tables of Changes. 56 Intel® Pentium® 4 Processor on the originating bus (rather than in reaction to the transaction type and snoop results source. Status: For the ... Memory 64 Technology (Intel® EM64T) Problem: In an Intel® EM64T enabled Processor, the L-bit of the Code Segment (CS) descriptor may occur in a small window when one logical processor is making a transition from the addressed cache line in an HT environment. This may not...