Specification Update
Page 7
... unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the next release of the specifications. These changes will be taken to deviate from the current published specifications. Errata may cause the Intel® Celeron® processor in the next release...should be incorporated in the processor identification information table. These changes will be incorporated in the 478-Pin Package Specification Update 7 Intel® Celeron® Processor in the next release of the specifications. These clarifications will be incorporated in the...
... unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the next release of the specifications. These changes will be taken to deviate from the current published specifications. Errata may cause the Intel® Celeron® processor in the next release...should be incorporated in the processor identification information table. These changes will be incorporated in the 478-Pin Package Specification Update 7 Intel® Celeron® Processor in the next release of the specifications. These clarifications will be incorporated in the...
Specification Update
Page 9
... Process in Micro-FCPGA Package W= Intel® Celeron® M processor X = Intel® Pentium® M processor on 90nm process with 2-MB L2 Cache Y = Intel® Pentium® M processor Z = Mobile Intel ® Pentium ® 4 processor with 1MB L2 Cache K = Mobile Intel ® Pentium ® III processor L = Intel ® Celeron ® D processor M = Mobile Intel ® Celeron ® processor N = Intel ® Pentium ® 4 processor O = Intel ® Xeon™ processor MP...
... Process in Micro-FCPGA Package W= Intel® Celeron® M processor X = Intel® Pentium® M processor on 90nm process with 2-MB L2 Cache Y = Intel® Pentium® M processor Z = Mobile Intel ® Pentium ® 4 processor with 1MB L2 Cache K = Mobile Intel ® Pentium ® III processor L = Intel ® Celeron ® D processor M = Mobile Intel ® Celeron ® processor N = Intel ® Pentium ® 4 processor O = Intel ® Xeon™ processor MP...
Specification Update
Page 11
... Incorrect Changes to 0xDC001000 may cause IO and Special Cycle failure Fixed Erroneous BIST result found in the 478-Pin Package Specification Update 11 Summary Tables of the Resume Flag (RF Flag) in a Task-State...Bus Read-Invalidate Line (BRIL) Processor Does not Flag #GP on Non-zero Write to Certain MSRs L2 cache may contain stale data in the Exclusive state Simultaneous assertion of A20M# and INIT# may result in ... Provides a 4-Byte Store Unlock After an 8-Byte Load Lock Intel® Celeron® Processor in EAX register after reset NoFix NoFix NoFix The State of Changes R NO.
... Incorrect Changes to 0xDC001000 may cause IO and Special Cycle failure Fixed Erroneous BIST result found in the 478-Pin Package Specification Update 11 Summary Tables of the Resume Flag (RF Flag) in a Task-State...Bus Read-Invalidate Line (BRIL) Processor Does not Flag #GP on Non-zero Write to Certain MSRs L2 cache may contain stale data in the Exclusive state Simultaneous assertion of A20M# and INIT# may result in ... Provides a 4-Byte Store Unlock After an 8-Byte Load Lock Intel® Celeron® Processor in EAX register after reset NoFix NoFix NoFix The State of Changes R NO.
Specification Update
Page 15
...after the CPUID instruction is executed with a 1 in the EAX register. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL69Z E0 ...1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 1, 2 1 2, 3 3 2, 4, 8 2, 4 4 Intel® Celeron® Processor in the 478-pn package processor may be identified by the following values. Table 1. Family1 Model2 Brand3 1111b 1111b 0001b 0010b 00001010b 00001010b NOTES: 1. The Brand...
...after the CPUID instruction is executed with a 1 in the EAX register. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL69Z E0 ...1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 1, 2 1 2, 3 3 2, 4, 8 2, 4 4 Intel® Celeron® Processor in the 478-pn package processor may be identified by the following values. Table 1. Family1 Model2 Brand3 1111b 1111b 0001b 0010b 00001010b 00001010b NOTES: 1. The Brand...
Specification Update
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Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6RV C1 SL6VR D1 SL6VY D1 SL6RT C1 SL6RS ... 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 4, 8, 9 4, 8, 9 2, 4, 8 2, 5 5, 8, 10 5, 8, 9 2, 5, 8 2, 5, 8 2, 5, 8 2, 6 6, 8 6, 8, 9 2, 6, 8 6, 8, 9 16 Intel® Celeron® Processor in the 478-Pin Package Specification Update Component Identification Information R Table 1.
Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6RV C1 SL6VR D1 SL6VY D1 SL6RT C1 SL6RS ... 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 4, 8, 9 4, 8, 9 2, 4, 8 2, 5 5, 8, 10 5, 8, 9 2, 5, 8 2, 5, 8 2, 5, 8 2, 6 6, 8 6, 8, 9 2, 6, 8 6, 8, 9 16 Intel® Celeron® Processor in the 478-Pin Package Specification Update Component Identification Information R Table 1.
Specification Update
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...Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6W2 D1 SL6XJ C1 SL6WC D1 SL6WD D1 SL6T2 C1 SL6T5 C1 SL6VU C1 SL6W4 D1 SL6XG C1 SL6V2 C1 SL6VU...PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 2, 6, 8 6, 8 6, 8, 9 2, 6, 8 2, 6 2, 6, 8 7, 8 2, 7, 8 7, 8, 9 7, 8 7, 8 8 2, 8, 11 2, 8, 11 Intel® Celeron® Processor in the 478-Pin Package Specification Update 17 Component Identification Information R Table 1.
...Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6W2 D1 SL6XJ C1 SL6WC D1 SL6WD D1 SL6T2 C1 SL6T5 C1 SL6VU C1 SL6W4 D1 SL6XG C1 SL6V2 C1 SL6VU...PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 2, 6, 8 6, 8 6, 8, 9 2, 6, 8 2, 6 2, 6, 8 7, 8 2, 7, 8 7, 8, 9 7, 8 7, 8 8 2, 8, 11 2, 8, 11 Intel® Celeron® Processor in the 478-Pin Package Specification Update 17 Component Identification Information R Table 1.
Specification Update
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...176;C 5. This processor has maximum Tcase of 72 °C § Notes 8, 11 2, 8 8 8, 9 2, 8 2,8 2,8 18 Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6VV C1 SL77U D1 SL77S D1 SL77T D1 SL77V...0F29h 0F29h 0F29h 2.60 GHz/ 400 MHz 2.70 GHz/ 400 MHz 2.70 GHz/ 400 MHz 2.80 GHz/ 400 MHz 2.80 GHz/ 400 MHz 1.60GHz/400MHz 1.80GHz/400MHz FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev ...
...176;C 5. This processor has maximum Tcase of 72 °C § Notes 8, 11 2, 8 8 8, 9 2, 8 2,8 2,8 18 Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6VV C1 SL77U D1 SL77S D1 SL77T D1 SL77V...0F29h 0F29h 0F29h 2.60 GHz/ 400 MHz 2.70 GHz/ 400 MHz 2.70 GHz/ 400 MHz 2.80 GHz/ 400 MHz 2.80 GHz/ 400 MHz 1.60GHz/400MHz 1.80GHz/400MHz FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev ...
Specification Update
Page 23
...Contain Incorrect Information for Correctable Errors Problem: When a speculative load operation hits the L2 cache and receives a correctable error, the IA32_MC1_STATUS register may be asserted until this ...not be affected. AC13. For uncorrectable errors, the other fields in the 478-Pin Package Specification Update 23 Workaround: None identified. Since the lower 32 ... errors. Workaround: Since this erratum occurs, the IA32_MC0_STATUS register contains stale information. Intel® Celeron® Processor in the IA32_MC0_STATUS register are read when running, a possible workaround ...
...Contain Incorrect Information for Correctable Errors Problem: When a speculative load operation hits the L2 cache and receives a correctable error, the IA32_MC1_STATUS register may be asserted until this ...not be affected. AC13. For uncorrectable errors, the other fields in the 478-Pin Package Specification Update 23 Workaround: None identified. Since the lower 32 ... errors. Workaround: Since this erratum occurs, the IA32_MC0_STATUS register contains stale information. Intel® Celeron® Processor in the IA32_MC0_STATUS register are read when running, a possible workaround ...
Specification Update
Page 25
...Machine Check Architecture (MCA) Bank 2 by setting all IA32_MC2_CTL register bits to 0, uncorrectable errors should be generated. Intel® Celeron® Processor in the L2 cache, IA32_MC0_STATUS.UNCOR and IA32_MC0_STATUS.PCC are not logged. • When one error has been received. No data loss...MCE) is subsequently accessed, an MCE will hang. • When a hardware prefetch results in an uncorrectable tag error in the 478-Pin Package Specification Update 25 Implication: The processor is blocked, and the processor will occur. Workaround: None identified. Status: For ...
...Machine Check Architecture (MCA) Bank 2 by setting all IA32_MC2_CTL register bits to 0, uncorrectable errors should be generated. Intel® Celeron® Processor in the L2 cache, IA32_MC0_STATUS.UNCOR and IA32_MC0_STATUS.PCC are not logged. • When one error has been received. No data loss...MCE) is subsequently accessed, an MCE will hang. • When a hardware prefetch results in an uncorrectable tag error in the 478-Pin Package Specification Update 25 Implication: The processor is blocked, and the processor will occur. Workaround: None identified. Status: For ...
Specification Update
Page 30
...Intel® Celeron® Processor in the page directory or page table entries, the processor sends an 8-byte load lock onto the system bus. Implication: No known commercially available chipsets are affected by this erratum occurs, cache may become out of Changes. Multiple Accesses to the Same S-State L2 Cache... Line and ECC Error Combination May Result in Loss of Cache Coherency Problem: When a Read for Locked Operation Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the 478-Pin...
...Intel® Celeron® Processor in the page directory or page table entries, the processor sends an 8-byte load lock onto the system bus. Implication: No known commercially available chipsets are affected by this erratum occurs, cache may become out of Changes. Multiple Accesses to the Same S-State L2 Cache... Line and ECC Error Combination May Result in Loss of Cache Coherency Problem: When a Read for Locked Operation Problem: When the processor is in the Page Address Extension (PAE) mode and detects the need to set the Access and/or Dirty bits in the 478-Pin...
Specification Update
Page 33
... the further conditions occur: 4. An RFO to the 0xFFFFFXXX memory region, with HIT# and fills data in the L2 cache. Intel® Celeron® Processor in the L2 cache and its associated second-sector pre-fetch into an almost full bus queue, 2. A read to cacheline B completes.... Workaround: Deasserting and reasserting A20M# prior to unpredictable program execution. L2 Cache May Contain Stale Data in the Exclusive State Problem: If a cacheline (A) is in the Invalid (I ) state in the 478-Pin Package Specification Update 33 Implication: Stale data may fetch incorrect data...
... the further conditions occur: 4. An RFO to the 0xFFFFFXXX memory region, with HIT# and fills data in the L2 cache. Intel® Celeron® Processor in the L2 cache and its associated second-sector pre-fetch into an almost full bus queue, 2. A read to cacheline B completes.... Workaround: Deasserting and reasserting A20M# prior to unpredictable program execution. L2 Cache May Contain Stale Data in the Exclusive State Problem: If a cacheline (A) is in the Invalid (I ) state in the 478-Pin Package Specification Update 33 Implication: Stale data may fetch incorrect data...