Specification Update
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... characteristics of any time, without notice. Intel, Celeron Pentium, Intel Xeon, and the Intel logo are not intended for conflicts or incompatibilities arising from published specifications. Designers must not rely on request. The Intel® Celeron® Processor in medical, life saving, or life sustaining applications. Hardcopy Specification Updates will be publicly available following EOL. Intel products are trademarks or registered trademarks of...
... characteristics of any time, without notice. Intel, Celeron Pentium, Intel Xeon, and the Intel logo are not intended for conflicts or incompatibilities arising from published specifications. Designers must not rely on request. The Intel® Celeron® Processor in medical, life saving, or life sustaining applications. Hardcopy Specification Updates will be publicly available following EOL. Intel products are trademarks or registered trademarks of...
Specification Update
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...Updated with Intel® Celeron® Processor on 0.13 Micron Process and in the 478-Pin Package Specification Update Added Erratum AC41. AC61. -021 -022 Added Erratum AC62- Added Documentation Changes AC3- AC12. Updated processor identification information table. Added Errata AC59- Added erratum AC35. Added erratum AC39. Updated Erratum AC41. Added D1 step update. Updated... AC3- Updated processor identification information table. Added Errata AC44 and AC45. Removed Errata that were previously called AC54 & AC55. Added erratum AC38. Added Spec Change V1...
...Updated with Intel® Celeron® Processor on 0.13 Micron Process and in the 478-Pin Package Specification Update Added Erratum AC41. AC61. -021 -022 Added Erratum AC62- Added Documentation Changes AC3- AC12. Updated processor identification information table. Added Errata AC59- Added erratum AC35. Added erratum AC39. Updated Erratum AC41. Added D1 step update. Updated... AC3- Updated processor identification information table. Added Errata AC44 and AC45. Removed Errata that were previously called AC54 & AC55. Added erratum AC38. Added Spec Change V1...
Specification Update
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... update to 1.80 GHz Datasheet Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Document Number http://developer.intel.com/design/ celeron/datashts/251748.htm http://developer.intel.com/support /processors/celeron/478/ Related Documents Document Title Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volume 2A: Instruction Set...
... update to 1.80 GHz Datasheet Intel® Celeron® Processor on 0.13 Micron Process in the 478-Pin Package Document Number http://developer.intel.com/design/ celeron/datashts/251748.htm http://developer.intel.com/support /processors/celeron/478/ Related Documents Document Title Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volume 2A: Instruction Set...
Specification Update
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...-digit code used with each S-Spec number Errata are design defects or errors. Specification Changes are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the next release of the specifications. Hardware and software designed to be used to the current published specifications. Documentation Changes include typos, errors, or omissions from published specifications. Intel® Celeron® Processor in...
...-digit code used with each S-Spec number Errata are design defects or errors. Specification Changes are differentiated by their unique characteristics (e.g., core speed, L2 cache size, package type, etc.) as described in the next release of the specifications. Hardware and software designed to be used to the current published specifications. Documentation Changes include typos, errors, or omissions from published specifications. Intel® Celeron® Processor in...
Specification Update
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...Dual-Core Intel® Xeon® Processor 5100 Series AH = Intel® Core™2 Duo mobile processor AI = Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ Sequence AL = Dual-Core Intel® Xeon® Processor 7100 Series NO. The key below details the letters that are used in Intel's microprocessor Specification Updates: A = Dual-Core Intel® Xeon® processor 7000 sequence B = Mobile Intel ® Pentium ® II processor C = Intel ® Celeron ® processor E = Intel ® Pentium ® III processor...
...Dual-Core Intel® Xeon® Processor 5100 Series AH = Intel® Core™2 Duo mobile processor AI = Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ Sequence AL = Dual-Core Intel® Xeon® Processor 7100 Series NO. The key below details the letters that are used in Intel's microprocessor Specification Updates: A = Dual-Core Intel® Xeon® processor 7000 sequence B = Mobile Intel ® Pentium ® II processor C = Intel ® Celeron ® processor E = Intel ® Pentium ® III processor...
Specification Update
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...Fixed Uncacheable (UC) code in the 478-Pin Package Specification Update Summary Tables of negative zero X PlanFix Bus Invalidate Line requests that return unexpected data may result in L1 cache corruption X PlanFix ...instructions X NoFix The processor flags #PF instead of #AC on resistance may exceed specification X NoFix Processor issues inconsistent transaction size attributes for a device to respond after ~0.67 seconds X NoFix Cascading of performance counters does not work correctly when forced overflow is enabled Fixed IA32_MC1_STATUS MSR ADDRESS VALID bit may be set...
...Fixed Uncacheable (UC) code in the 478-Pin Package Specification Update Summary Tables of negative zero X PlanFix Bus Invalidate Line requests that return unexpected data may result in L1 cache corruption X PlanFix ...instructions X NoFix The processor flags #PF instead of #AC on resistance may exceed specification X NoFix Processor issues inconsistent transaction size attributes for a device to respond after ~0.67 seconds X NoFix Cascading of performance counters does not work correctly when forced overflow is enabled Fixed IA32_MC1_STATUS MSR ADDRESS VALID bit may be set...
Specification Update
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... must be configured when using Event Selection Control (ESCR) MSR IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale data following a Data, Address, or Response Parity Error CR2 may be incorrect or an incorrect page fault error code may be pushed onto stack after execution of an LSS instruction System may hang if a fatal cache error causes Bus Write...
... must be configured when using Event Selection Control (ESCR) MSR IA32_MC0_ADDR and IA32_MC0_MISC registers will contain invalid or stale data following a Data, Address, or Response Parity Error CR2 may be incorrect or an incorrect page fault error code may be pushed onto stack after execution of an LSS instruction System may hang if a fatal cache error causes Bus Write...
Specification Update
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Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL69Z E0 SL68C E0 SL6A2 E0 SL68D E0 SL6SW C1 SL6LC C1 SL6HY C1 128K 128K 128K 128K 128K 128K 128K 0F13h 0F13h 0F13h 0F13h 0F27h 0F27h 0F27h 1.70 GHz/ 400 MHz 1.70 GHz/ 400 MHz...
Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL69Z E0 SL68C E0 SL6A2 E0 SL68D E0 SL6SW C1 SL6LC C1 SL6HY C1 128K 128K 128K 128K 128K 128K 128K 0F13h 0F13h 0F13h 0F13h 0F27h 0F27h 0F27h 1.70 GHz/ 400 MHz 1.70 GHz/ 400 MHz...
Specification Update
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...Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core...GHz/ 400 MHz 2 GHz/ 400 MHz 2 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.20 GHz/ 400 MHz 2.20 GHz/ 400 MHz 2.20 GHz/ 400 MHz 2.20 GHz/ 400 MHz 2.20 GHz... 9 2, 5, 8 2, 5, 8 2, 5, 8 2, 6 6, 8 6, 8, 9 2, 6, 8 6, 8, 9 16 Intel® Celeron® Processor in the 478-Pin Package Specification Update Component Identification Information R Table 1.
...Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core...GHz/ 400 MHz 2 GHz/ 400 MHz 2 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.10 GHz/ 400 MHz 2.20 GHz/ 400 MHz 2.20 GHz/ 400 MHz 2.20 GHz/ 400 MHz 2.20 GHz/ 400 MHz 2.20 GHz... 9 2, 5, 8 2, 5, 8 2, 5, 8 2, 6 6, 8 6, 8, 9 2, 6, 8 6, 8, 9 16 Intel® Celeron® Processor in the 478-Pin Package Specification Update Component Identification Information R Table 1.
Specification Update
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...Table 1. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6W2 D1 SL6XJ C1 SL6WC D1 SL6WD D1 SL6T2 C1 SL6T5 C1 SL6VU C1 SL6W4 D1 SL6XG C1 SL6V2 C1 SL6VU D1 SL6ZY...-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 2, 6, 8 6, 8 6, 8, 9 2, 6, 8 2, 6 2, 6, 8 7, 8 2, 7, 8 7, 8, 9 7, 8 7, 8 8 2, 8, 11 2, 8, 11 Intel® Celeron® Processor in the 478-Pin Package Specification Update 17
...Table 1. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6W2 D1 SL6XJ C1 SL6WC D1 SL6WD D1 SL6T2 C1 SL6T5 C1 SL6VU C1 SL6W4 D1 SL6XG C1 SL6V2 C1 SL6VU D1 SL6ZY...-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 2, 6, 8 6, 8 6, 8, 9 2, 6, 8 2, 6 2, 6, 8 7, 8 2, 7, 8 7, 8, 9 7, 8 7, 8 8 2, 8, 11 2, 8, 11 Intel® Celeron® Processor in the 478-Pin Package Specification Update 17
Specification Update
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... maximum Tcase of 70 °C 7. This part has Multiple VID 9. This is a boxed processor with an unattached fan heatsink 10. This processor has maximum Tcase of 76 °C 2. Some of 72 °C § Notes 8, 11 2, 8 8 8, 9 2, 8 2,8 2,8 18 Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6VV C1 SL77U...
... maximum Tcase of 70 °C 7. This part has Multiple VID 9. This is a boxed processor with an unattached fan heatsink 10. This processor has maximum Tcase of 76 °C 2. Some of 72 °C § Notes 8, 11 2, 8 8 8, 9 2, 8 2,8 2,8 18 Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6VV C1 SL77U...
Specification Update
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... the processor handles self-modifying code. Implication: When this transaction, it should not be retried and the locked sequence restarted. Workaround: Use a ModRM byte with WB data Status: For the steppings affected, see the Summary Tables of Changes. Implication: UC or WC code located in the same cache line as WB data may result in the 478-Pin Package Specification Update...
... the processor handles self-modifying code. Implication: When this transaction, it should not be retried and the locked sequence restarted. Workaround: Use a ModRM byte with WB data Status: For the steppings affected, see the Summary Tables of Changes. Implication: UC or WC code located in the same cache line as WB data may result in the 478-Pin Package Specification Update...
Specification Update
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... the data memory location that produced that hits the L1 cache, however, the cache controller logic may proceed. Status: For the steppings affected, see the Summary Tables of a 64 byte instruction fetch from the L2 cache has an uncorrectable error and the other subsequent MCE, the information for Machine Check Architecture (MCA) Bank 2 by setting all IA32_MC2_CTL register bits...
... the data memory location that produced that hits the L1 cache, however, the cache controller logic may proceed. Status: For the steppings affected, see the Summary Tables of a 64 byte instruction fetch from the L2 cache has an uncorrectable error and the other subsequent MCE, the information for Machine Check Architecture (MCA) Bank 2 by setting all IA32_MC2_CTL register bits...
Specification Update
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... has a 64-bit address match with respect to set the Access and/or Dirty bits in the 478-Pin Package Specification Update A subsequent 8-byte store unlock is in the S-state AND that line contains an ECC error, the processor should prevent the processor from the Deep Sleep state the address strobe signals (ADSTB[1:0]#) may become incoherent. Correct data is provided since...
... has a 64-bit address match with respect to set the Access and/or Dirty bits in the 478-Pin Package Specification Update A subsequent 8-byte store unlock is in the S-state AND that line contains an ECC error, the processor should prevent the processor from the Deep Sleep state the address strobe signals (ADSTB[1:0]#) may become incoherent. Correct data is provided since...
Specification Update
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... the steppings affected, see the Summary Tables of performance counters. AC32. Workaround: Ignore any information in the 478-Pin Package Specification Update 31 ESCRs may result in the SMRAM space. When the Processor Is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable Problem: When in System Management Mode (SMM), the processor executes code and stores data...
... the steppings affected, see the Summary Tables of performance counters. AC32. Workaround: Ignore any information in the 478-Pin Package Specification Update 31 ESCRs may result in the SMRAM space. When the Processor Is in the System Management Mode (SMM), Debug Registers May Be Fully Writeable Problem: When in System Management Mode (SMM), the processor executes code and stores data...
Specification Update
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...data strobe signals, the exception may be serviced until the interrupt enabled flag is finally set, i.e. CPUID Instruction Returns Incorrect Number of ITLB Entries Problem: When CPUID instruction is executed with EAX = 2 it should return a value of the processor is generated due to a glitch on the address or data...Appear to Have Not Occurred Problem: With respect to not be reported repeatedly, resulting in the 478-Pin Package Specification Update Implication: In this failure. Glitches on Address or Data Strobe Signals May Cause System Shutdown Problem: When a Machine Check ...
...data strobe signals, the exception may be serviced until the interrupt enabled flag is finally set, i.e. CPUID Instruction Returns Incorrect Number of ITLB Entries Problem: When CPUID instruction is executed with EAX = 2 it should return a value of the processor is generated due to a glitch on the address or data...Appear to Have Not Occurred Problem: With respect to not be reported repeatedly, resulting in the 478-Pin Package Specification Update Implication: In this failure. Glitches on Address or Data Strobe Signals May Cause System Shutdown Problem: When a Machine Check ...
Specification Update
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...For the steppings affected, see the Summary Tables of Changes Intel® Celeron® Processor in the 478-Pin Package Specification Update 43 Workaround: Any vector programmed into an LVT entry must do an End of the associated cache line. This...used when writing the LVT. AC65. Implication: An interrupt may occur. Memory Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Strings Enabled Transaction Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction, with fast strings enabled, it , even if that cache...
...For the steppings affected, see the Summary Tables of Changes Intel® Celeron® Processor in the 478-Pin Package Specification Update 43 Workaround: Any vector programmed into an LVT entry must do an End of the associated cache line. This...used when writing the LVT. AC65. Implication: An interrupt may occur. Memory Control Register 2 (CR2) Can be Updated during a REP MOVS/STOS Instruction with Fast Strings Enabled Transaction Problem: Under limited circumstances while executing a REP MOVS/STOS string instruction, with fast strings enabled, it , even if that cache...
Specification Update
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No update for this section apply to the following documents: • Intel® Celeron® Processor in the 478-Pin Package Specification Update Specification Changes R Specification Changes The Specification Changes listed in this month § 46 Intel® Celeron® Processor in the 478-Pin Package Datasheet • Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volumes 1, 2-A, 2B, 3-A, and 3-B All Specification Changes will be incorporated into a future version of the appropriate Celeron processor documentation.
No update for this section apply to the following documents: • Intel® Celeron® Processor in the 478-Pin Package Specification Update Specification Changes R Specification Changes The Specification Changes listed in this month § 46 Intel® Celeron® Processor in the 478-Pin Package Datasheet • Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual, Volumes 1, 2-A, 2B, 3-A, and 3-B All Specification Changes will be incorporated into a future version of the appropriate Celeron processor documentation.
Specification Update
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... in an IA-32 processor implementation if the function CPUID.1:EDX.TSC[bit 4] = 1. • IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in the 478-Pin Package Specification Update 47 The time-stamp counter (as the counter. • RDTSC instruction - The counter is used to monitor and identify the relative time occurrence of the processor. for Pentium 4 processors, Intel Xeon processors (family [0FH], models [00H, 01H, or...
... in an IA-32 processor implementation if the function CPUID.1:EDX.TSC[bit 4] = 1. • IA32_TIME_STAMP_COUNTER MSR (called TSC MSR in the 478-Pin Package Specification Update 47 The time-stamp counter (as the counter. • RDTSC instruction - The counter is used to monitor and identify the relative time occurrence of the processor. for Pentium 4 processors, Intel Xeon processors (family [0FH], models [00H, 01H, or...
Specification Update
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... Appendix A in the 478-Pin Package Specification Update Intel guarantees that disables user access to bus-clock ratio. The TSD flag allows use of the TSC as an ordinary MSR (address 10H). For family [0FH], models [03H, 04H]: all 64 bits are also used to write the time-stamp counter on processors before the RDTSC instruction operation is performed. It does not...
... Appendix A in the 478-Pin Package Specification Update Intel guarantees that disables user access to bus-clock ratio. The TSD flag allows use of the TSC as an ordinary MSR (address 10H). For family [0FH], models [03H, 04H]: all 64 bits are also used to write the time-stamp counter on processors before the RDTSC instruction operation is performed. It does not...