Specification Update
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... same line as write back (WB) data may lead to data corruption X NoFix Transaction is not retried after BINIT# X NoFix Invalid opcode 0FFFh requires a ModRM byte X NoFix FSW may not be completely restored after page fault on FRSTOR or FLDENV instructions X NoFix The processor flags #PF instead of #AC on an... are in Write Combining (WC) memory space PlanFix Buffer on resistance may exceed specification X NoFix Processor issues inconsistent transaction size attributes for locked operation 10 Intel® Celeron® Processor in the 478-Pin Package Specification Update
... same line as write back (WB) data may lead to data corruption X NoFix Transaction is not retried after BINIT# X NoFix Invalid opcode 0FFFh requires a ModRM byte X NoFix FSW may not be completely restored after page fault on FRSTOR or FLDENV instructions X NoFix The processor flags #PF instead of #AC on an... are in Write Combining (WC) memory space PlanFix Buffer on resistance may exceed specification X NoFix Processor issues inconsistent transaction size attributes for locked operation 10 Intel® Celeron® Processor in the 478-Pin Package Specification Update
Specification Update
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... ITLB Entries A Write to an APIC Register Sometimes May Appear to Have Not Occurred Store to Load Data Forwarding may Result in Switched Data Bytes Parity Error in the L1 Cache may Cause the Processor to Hang The TCK Input in the Test Access Port (TAP) is Sensitive to ... address to a value less than or equal to CR3 Register do not Fence Pending Instruction Page Walks Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock Intel® Celeron® Processor in the 478-Pin Package Specification Update 11 Summary Tables of the Resume Flag (RF Flag) in a Task-State Segment (TSS) May...
... ITLB Entries A Write to an APIC Register Sometimes May Appear to Have Not Occurred Store to Load Data Forwarding may Result in Switched Data Bytes Parity Error in the L1 Cache may Cause the Processor to Hang The TCK Input in the Test Access Port (TAP) is Sensitive to ... address to a value less than or equal to CR3 Register do not Fence Pending Instruction Page Walks Processor Provides a 4-Byte Store Unlock After an 8-Byte Load Lock Intel® Celeron® Processor in the 478-Pin Package Specification Update 11 Summary Tables of the Resume Flag (RF Flag) in a Task-State Segment (TSS) May...
Specification Update
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.... Family1 Model2 Brand3 1111b 1111b 0001b 0010b 00001010b 00001010b NOTES: 1. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL69Z E0 SL68C E0...1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 1, 2 1 2, 3 3 2, 4, 8 2, 4 4 Intel® Celeron® Processor in the 478-pn package processor may be identified by the following values. The Brand ID corresponds to bits [7:4] of the EDX register after RESET, bits...
.... Family1 Model2 Brand3 1111b 1111b 0001b 0010b 00001010b 00001010b NOTES: 1. Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL69Z E0 SL68C E0...1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 1, 2 1 2, 3 3 2, 4, 8 2, 4 4 Intel® Celeron® Processor in the 478-pn package processor may be identified by the following values. The Brand ID corresponds to bits [7:4] of the EDX register after RESET, bits...
Specification Update
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Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6RV C1 SL6VR D1 SL6VY D1 SL6RT C1 SL6RS C1 ...31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 4, 8, 9 4, 8, 9 2, 4, 8 2, 5 5, 8, 10 5, 8, 9 2, 5, 8 2, 5, 8 2, 5, 8 2, 6 6, 8 6, 8, 9 2, 6, 8 6, 8, 9 16 Intel® Celeron® Processor in the 478-Pin Package Specification Update Component Identification Information R Table 1.
Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6RV C1 SL6VR D1 SL6VY D1 SL6RT C1 SL6RS C1 ...31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 4, 8, 9 4, 8, 9 2, 4, 8 2, 5 5, 8, 10 5, 8, 9 2, 5, 8 2, 5, 8 2, 5, 8 2, 6 6, 8 6, 8, 9 2, 6, 8 6, 8, 9 16 Intel® Celeron® Processor in the 478-Pin Package Specification Update Component Identification Information R Table 1.
Specification Update
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...Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6W2 D1 SL6XJ C1 SL6WC D1 SL6WD D1 SL6T2 C1 SL6T5 C1 SL6VU C1 SL6W4 D1 SL6XG C1 SL6V2 C1 SL6VU...PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 2, 6, 8 6, 8 6, 8, 9 2, 6, 8 2, 6 2, 6, 8 7, 8 2, 7, 8 7, 8, 9 7, 8 7, 8 8 2, 8, 11 2, 8, 11 Intel® Celeron® Processor in the 478-Pin Package Specification Update 17 Component Identification Information R Table 1.
...Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6W2 D1 SL6XJ C1 SL6WC D1 SL6WD D1 SL6T2 C1 SL6T5 C1 SL6VU C1 SL6W4 D1 SL6XG C1 SL6V2 C1 SL6VU...PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 Notes 2, 6, 8 6, 8 6, 8, 9 2, 6, 8 2, 6 2, 6, 8 7, 8 2, 7, 8 7, 8, 9 7, 8 7, 8 8 2, 8, 11 2, 8, 11 Intel® Celeron® Processor in the 478-Pin Package Specification Update 17 Component Identification Information R Table 1.
Specification Update
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... 1. This processor has maximum Tcase of 72 °C § Notes 8, 11 2, 8 8 8, 9 2, 8 2,8 2,8 18 Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6VV C1 SL77U D1 SL77S D1 SL77T D1 SL77V...0F29h 0F29h 0F29h 2.60 GHz/ 400 MHz 2.70 GHz/ 400 MHz 2.70 GHz/ 400 MHz 2.80 GHz/ 400 MHz 2.80 GHz/ 400 MHz 1.60GHz/400MHz 1.80GHz/400MHz FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev ...
... 1. This processor has maximum Tcase of 72 °C § Notes 8, 11 2, 8 8 8, 9 2, 8 2,8 2,8 18 Intel® Celeron® Processor in the 478-Pin Package Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Speed Core/Bus Package and Revision SL6VV C1 SL77U D1 SL77S D1 SL77T D1 SL77V...0F29h 0F29h 0F29h 2.60 GHz/ 400 MHz 2.70 GHz/ 400 MHz 2.70 GHz/ 400 MHz 2.80 GHz/ 400 MHz 2.80 GHz/ 400 MHz 1.60GHz/400MHz 1.80GHz/400MHz FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev 1.0 FC-PGA2 31.0 mm , rev ...
Specification Update
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...: UC or WC code should be retried. AC5. Status: For the steppings affected, see the Summary Tables of Changes. 20 Intel® Celeron® Processor in the Intel® Pentium® 4 processor. The data supplied by this erratum occurs, locked transactions will unexpectedly not be retried and the locked... line, the UC fetch will not be corrupted due to data corruption. The invalid opcode 0FFFh did not require a ModRM byte in previous generation Intel® architecture processors, but does in the 478-Pin Package Specification Update Implication: The use of Changes.
...: UC or WC code should be retried. AC5. Status: For the steppings affected, see the Summary Tables of Changes. 20 Intel® Celeron® Processor in the Intel® Pentium® 4 processor. The data supplied by this erratum occurs, locked transactions will unexpectedly not be retried and the locked... line, the UC fetch will not be corrupted due to data corruption. The invalid opcode 0FFFh did not require a ModRM byte in previous generation Intel® architecture processors, but does in the 478-Pin Package Specification Update Implication: The use of Changes.
Specification Update
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... the software's dependency on the instruction near the wrap boundary, the upper byte of the FPU status word (FSW) might not be flagged. AC8. ...Software that depends #AC before #PF will be restored. Alternately, reload the page in the 478-Pin Package Specification Update 21 Implication: When this case. Alternately, ensure that the page fault handler... FSW. AC7. Workaround: None identified. By forcing the memory type of the MTRR settings. Intel® Celeron® Processor in the page fault handler and then restart the faulting instruction. Status: For the...
... the software's dependency on the instruction near the wrap boundary, the upper byte of the FPU status word (FSW) might not be flagged. AC8. ...Software that depends #AC before #PF will be restored. Alternately, reload the page in the 478-Pin Package Specification Update 21 Implication: When this case. Alternately, ensure that the page fault handler... FSW. AC7. Workaround: None identified. By forcing the memory type of the MTRR settings. Intel® Celeron® Processor in the page fault handler and then restart the faulting instruction. Status: For the...
Specification Update
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...: 1) An FLD instruction signals a stack overflow or underflow, 2) the FLD instruction splits a page-boundary or a 64-byte cache line boundary, 3) the instruction matches a Debug Register on the high page or cache line respectively, and 4) the FLD... load, and avoiding serialized instructions before the UC load will reduce the occurrence of Changes. 24 Intel® Celeron® Processor in DR6 when the processor goes to an internal segment register access conflict. Implication:... Problem: Certain debug mechanisms may be reported in the 478-Pin Package Specification Update Errata R AC15.
...: 1) An FLD instruction signals a stack overflow or underflow, 2) the FLD instruction splits a page-boundary or a 64-byte cache line boundary, 3) the instruction matches a Debug Register on the high page or cache line respectively, and 4) the FLD... load, and avoiding serialized instructions before the UC load will reduce the occurrence of Changes. 24 Intel® Celeron® Processor in DR6 when the processor goes to an internal segment register access conflict. Implication:... Problem: Certain debug mechanisms may be reported in the 478-Pin Package Specification Update Errata R AC15.
Specification Update
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...of the data memory location that produced that more than one half of a 64 byte instruction fetch from a subsequent load or store operation into the IA32_MC1_ADDR register. Implication: ... hang. • When a hardware prefetch results in an uncorrectable tag error in the 478-Pin Package Specification Update 25 In the situations described below, the processor does not report ...8226; When a transaction is unable to report and/or recover from certain errors. Intel® Celeron® Processor in the L2 cache, IA32_MC0_STATUS.UNCOR and IA32_MC0_STATUS.PCC are not logged....
...of the data memory location that produced that more than one half of a 64 byte instruction fetch from a subsequent load or store operation into the IA32_MC1_ADDR register. Implication: ... hang. • When a hardware prefetch results in an uncorrectable tag error in the 478-Pin Package Specification Update 25 In the situations described below, the processor does not report ...8226; When a transaction is unable to report and/or recover from certain errors. Intel® Celeron® Processor in the L2 cache, IA32_MC0_STATUS.UNCOR and IA32_MC0_STATUS.PCC are not logged....
Specification Update
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... processor hang is controlled by interactions between thermal control circuit and floating-point event handler. Intel® Celeron® Processor in the IA32_MC1_STATUS MSR if a valid address is set . Implication: When...in the IA32_MC1_STATUS MSR should only log the address for L1 parity errors in the 478-Pin Package Specification Update 27 Errata R AC19. IA32_MC1_STATUS MSR ADDRESS VALID Bit May... Data Pointer (FDP) may be disabled. The processor stalls trying to fetch the bytes of the faulting floating-point instruction and those following it fails to count x87 loads...
... processor hang is controlled by interactions between thermal control circuit and floating-point event handler. Intel® Celeron® Processor in the IA32_MC1_STATUS MSR if a valid address is set . Implication: When...in the IA32_MC1_STATUS MSR should only log the address for L1 parity errors in the 478-Pin Package Specification Update 27 Errata R AC19. IA32_MC1_STATUS MSR ADDRESS VALID Bit May... Data Pointer (FDP) may be disabled. The processor stalls trying to fetch the bytes of the faulting floating-point instruction and those following it fails to count x87 loads...
Specification Update
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... failure conditions. Software could be accessed by the processor and hits a line in shared state in the 478-Pin Package Specification Update Bus Invalidate Line Requests That Return Unexpected Data May Result in L1 Cache Corruption Problem...as a 0 length Read-Invalidate (a BIL), since it doesn't need data, just ownership of Changes. 28 Intel® Celeron® Processor in the L1 cache. • The RFO is then issued on the system bus as operands... negative zero is returning to the processor. This store straddles an 8-byte boundary. • Due to eliminate the failure conditions.
... failure conditions. Software could be accessed by the processor and hits a line in shared state in the 478-Pin Package Specification Update Bus Invalidate Line Requests That Return Unexpected Data May Result in L1 Cache Corruption Problem...as a 0 length Read-Invalidate (a BIL), since it doesn't need data, just ownership of Changes. 28 Intel® Celeron® Processor in the L1 cache. • The RFO is then issued on the system bus as operands... negative zero is returning to the processor. This store straddles an 8-byte boundary. • Due to eliminate the failure conditions.
Specification Update
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...to the Same S-State L2 Cache Line and ECC Error Combination May Result in the 478-Pin Package Specification Update AC28. Status: For the steppings affected, see the Summary ...and attempts to the system bus clock (BCLK). Correct data is expected, but instead a 4-byte store unlock occurs. Implication: When this erratum. Workaround: The system BIOS should prevent the ...become incoherent. Status: For the steppings affected, see the Summary Tables of Changes. 30 Intel® Celeron® Processor in Loss of Cache Coherency Problem: When a Read for Locked Operation ...
...to the Same S-State L2 Cache Line and ECC Error Combination May Result in the 478-Pin Package Specification Update AC28. Status: For the steppings affected, see the Summary ...and attempts to the system bus clock (BCLK). Correct data is expected, but instead a 4-byte store unlock occurs. Implication: When this erratum. Workaround: The system BIOS should prevent the ...become incoherent. Status: For the steppings affected, see the Summary Tables of Changes. 30 Intel® Celeron® Processor in Loss of Cache Coherency Problem: When a Read for Locked Operation ...
Specification Update
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...may execute with incorrect data. Status: For the steppings affected, see the Summary Tables of this erratum with increases in the 478-Pin Package Specification Update 35 Other bus accesses are not affected. Status: For the steppings affected, see the Summary Tables of Changes....store, the resulting data forwarded from the store to minimize the TAP error rate. Intel® Celeron® Processor in background system noise. Store to Load Data Forwarding may Result in Switched Data Bytes Problem: If in a short window after an instruction that updates a segment register ...
...may execute with incorrect data. Status: For the steppings affected, see the Summary Tables of this erratum with increases in the 478-Pin Package Specification Update 35 Other bus accesses are not affected. Status: For the steppings affected, see the Summary Tables of Changes....store, the resulting data forwarded from the store to minimize the TAP error rate. Intel® Celeron® Processor in background system noise. Store to Load Data Forwarding may Result in Switched Data Bytes Problem: If in a short window after an instruction that updates a segment register ...
Specification Update
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... a system bus interrupt message with data (e.g. A subsequent 8 byte store unlock is expected, but will complete the operation so as not to the PDE portion of Changes Intel® Celeron® Processor in the 478-Pin Package Specification Update 37 Correct data is still in progress... receives a HardFailure response, a potential processor hang can occur. If a HardFailure response occurs on hardfailwithout-data, but instead a 4 byte store unlock occurs. Changes to CR3 Register Do Not Fence Pending Instruction Page Walks Problem: When software writes to an incorrect memory address...
... a system bus interrupt message with data (e.g. A subsequent 8 byte store unlock is expected, but will complete the operation so as not to the PDE portion of Changes Intel® Celeron® Processor in the 478-Pin Package Specification Update 37 Correct data is still in progress... receives a HardFailure response, a potential processor hang can occur. If a HardFailure response occurs on hardfailwithout-data, but instead a 4 byte store unlock occurs. Changes to CR3 Register Do Not Fence Pending Instruction Page Walks Problem: When software writes to an incorrect memory address...