Specification Update
Page 25
... stack frame. IO_SMI Indication in SMRAM's location 7FA4H is set to "1" by the CPU to this erratum with any commercially available software. The SMM handler must not restart an... code may be observed with IRET. LER MSRs May Be Unreliable Problem: Due to certain internal processor events, updates to the LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH... synchronous SMI for use with a software generated stack frame. BJ18. Workaround: None identified. Intel has not observed this erratum, the IO_SMI bit may be pushed onto the stack. Status...
... stack frame. IO_SMI Indication in SMRAM's location 7FA4H is set to "1" by the CPU to this erratum with any commercially available software. The SMM handler must not restart an... code may be observed with IRET. LER MSRs May Be Unreliable Problem: Due to certain internal processor events, updates to the LER (Last Exception Record) MSRs, MSR_LER_FROM_LIP (1DDH) and MSR_LER_TO_LIP (1DEH... synchronous SMI for use with a software generated stack frame. BJ18. Workaround: None identified. Intel has not observed this erratum, the IO_SMI bit may be pushed onto the stack. Status...
Specification Update
Page 30
...and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as UR (Unsupported Requests). Implication: The processor response to a critical error. Status: For the steppings affected, see the Summary Tables of Changes. Implication: The value of the 3 above ...of the LBR, BTS, and BTM immediately after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU will be incorrect. Due to this erratum, the integrated PCIe controller's root ports may not fully comply to the PCIe specification, should not...
...and the BTS (Branch Trace Store), hence rendering their data invalid. The corresponding data if sent out as UR (Unsupported Requests). Implication: The processor response to a critical error. Status: For the steppings affected, see the Summary Tables of Changes. Implication: The value of the 3 above ...of the LBR, BTS, and BTM immediately after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU will be incorrect. Due to this erratum, the integrated PCIe controller's root ports may not fully comply to the PCIe specification, should not...