Specification Update
Page 12
...Processor Behavior C-state Exit Latencies May be Higher Than Expected MSR_Temperature_Target May Have an Incorrect Value in the Temperature Control Offset Field Intel...Processor Creates a Valid Translation for a Page TSC Deadline Not Armed While in APIC Legacy Mode PCIe* Upstream TCfgWr May Cause Unpredictable System Behavior Processor... May Fail to Acknowledge a TLP Request Executing The GETSEC Instruction While Throttling May Result in a Processor Hang PerfMon...in TSC Deadline Mode RC6 Entry Can be Blocked by Asynchronous Intel® VT-d Flows Repeated PCIe* and/or DMI L1...
...Processor Behavior C-state Exit Latencies May be Higher Than Expected MSR_Temperature_Target May Have an Incorrect Value in the Temperature Control Offset Field Intel...Processor Creates a Valid Translation for a Page TSC Deadline Not Armed While in APIC Legacy Mode PCIe* Upstream TCfgWr May Cause Unpredictable System Behavior Processor... May Fail to Acknowledge a TLP Request Executing The GETSEC Instruction While Throttling May Result in a Processor Hang PerfMon...in TSC Deadline Mode RC6 Entry Can be Blocked by Asynchronous Intel® VT-d Flows Repeated PCIe* and/or DMI L1...
Specification Update
Page 13
... State May Not be Accurate After a Warm Reset Display Corruption May be Seen After Graphics Voltage Rail (VCC_AXG) Power Up PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit ...May Get Incorrect Count PDIR May Not Function Properly With FREEZE_PERFMON_ON_PMI For A Single Logical Processor Package, HTT May be Set to Zero Even Though The Package Reserves More Than... Using FREEZE_LBRS_ON_PMI A First Level Data Cache Parity Error May Result in Unexpected Behavior Intel® Trusted Execution Technology ACM Revocation Programming PDIR And an Additional Precise PerfMon Event...
... State May Not be Accurate After a Warm Reset Display Corruption May be Seen After Graphics Voltage Rail (VCC_AXG) Power Up PCMPESTRI, PCMPESTRM, VPCMPESTRI and VPCMPESTRM Always Operate with 32-bit ...May Get Incorrect Count PDIR May Not Function Properly With FREEZE_PERFMON_ON_PMI For A Single Logical Processor Package, HTT May be Set to Zero Even Though The Package Reserves More Than... Using FREEZE_LBRS_ON_PMI A First Level Data Cache Parity Error May Result in Unexpected Behavior Intel® Trusted Execution Technology ACM Revocation Programming PDIR And an Additional Precise PerfMon Event...
Specification Update
Page 45
...affected, see the Summary Tables of Presence Detect State bit (SLOTSTS Device 1; Offset BAH; bit [6]) may cause a nondeterministic state in the processor graphics logic. BJ84. No failures have been observed due to this erratum. PCIe* Presence Detect State May Not be accurate after a warm...check shutdown will occur. Workaround: A graphics driver workaround has been identified and may be Seen After Graphics Voltage Rail (VCC_AXG) Power Up Problem: Powering up the processor graphics logic in a system hang. Status: For the steppings affected, see the Summary Tables of BIST During...
...affected, see the Summary Tables of Presence Detect State bit (SLOTSTS Device 1; Offset BAH; bit [6]) may cause a nondeterministic state in the processor graphics logic. BJ84. No failures have been observed due to this erratum. PCIe* Presence Detect State May Not be accurate after a warm...check shutdown will occur. Workaround: A graphics driver workaround has been identified and may be Seen After Graphics Voltage Rail (VCC_AXG) Power Up Problem: Powering up the processor graphics logic in a system hang. Status: For the steppings affected, see the Summary Tables of BIST During...