Specification Update
Page 45
... to this erratum, BIST cannot be enabled. BJ83. Function 0,1,2; Offset BAH; Workaround: A graphics driver workaround has been identified and may be Seen After Graphics Voltage Rail (VCC_AXG) Power Up Problem: Powering up the processor graphics logic in the processor graphics logic. Specification Update 45 BJ81. BJ84. Display Corruption May be implemented as...
... to this erratum, BIST cannot be enabled. BJ83. Function 0,1,2; Offset BAH; Workaround: A graphics driver workaround has been identified and may be Seen After Graphics Voltage Rail (VCC_AXG) Power Up Problem: Powering up the processor graphics logic in the processor graphics logic. Specification Update 45 BJ81. BJ84. Display Corruption May be implemented as...
Specification Update
Page 48
... systems with FREEZE_PERFMON_ON_PMI, bit 11, in the IA32_DEBUGCTL MSR (1D9h), the processor may behave in AnyThread mode may count the same event on the same core. BJ92. Status: For the steppings affected, see the Summary Tables of Changes. Workaround: A software driver should not program FreezeOnPMI in AnyThread Mode May Get Incorrect Count Problem...
... systems with FREEZE_PERFMON_ON_PMI, bit 11, in the IA32_DEBUGCTL MSR (1D9h), the processor may behave in AnyThread mode may count the same event on the same core. BJ92. Status: For the steppings affected, see the Summary Tables of Changes. Workaround: A software driver should not program FreezeOnPMI in AnyThread Mode May Get Incorrect Count Problem...
Specification Update
Page 52
Workaround: The sampling driver should avoid using low SAV values, the program may return wrong PEBS/PMI interrupts and/or incorrect counter values if the counter is reset with a ... Problem: When the PDIR (Precise Distribution for Instructions Retired) mechanism is the counter reset value software programs in MSR IA32_PMC1[47:0] in PEBS mode), the processor may get incorrect PEBS or PMI interrupts and/or an invalid counter state.
Workaround: The sampling driver should avoid using low SAV values, the program may return wrong PEBS/PMI interrupts and/or incorrect counter values if the counter is reset with a ... Problem: When the PDIR (Precise Distribution for Instructions Retired) mechanism is the counter reset value software programs in MSR IA32_PMC1[47:0] in PEBS mode), the processor may get incorrect PEBS or PMI interrupts and/or an invalid counter state.