Data Sheet
Page 27
... the following: GTLREF_PU = 50 , GTLREF_PD = 100 3. The processor bus ratio multiplier will be provided on the board (for the processor supported ratios. The processor supports Half Ratios between 7.5 and 13.5, See Table 15 for Quad-Core processors compatibility) the two GTLREF lands connected to VSS. 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed...
... the following: GTLREF_PU = 50 , GTLREF_PD = 100 3. The processor bus ratio multiplier will be provided on the board (for the processor supported ratios. The processor supports Half Ratios between 7.5 and 13.5, See Table 15 for Quad-Core processors compatibility) the two GTLREF lands connected to VSS. 2.8 Clock Specifications 2.8.1 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking BCLK[1:0] directly controls the FSB interface speed...
Data Sheet
Page 87
...the level to return to the Normal State. When the processor exits the Extended HALT state, it will first switch to the lower bus ratio and then transition to the original value. Only one of the processor-issued Stop Grant Acknowledge special bus cycle. While in the ...Extended HALT state, the processor will cause the processor to the Normal state. Stop-Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor cores executes the HALT instruction, that the processor FSB frequency is changed...
...the level to return to the Normal State. When the processor exits the Extended HALT state, it will first switch to the lower bus ratio and then transition to the original value. Only one of the processor-issued Stop Grant Acknowledge special bus cycle. While in the ...Extended HALT state, the processor will cause the processor to the Normal state. Stop-Grant State When the STPCLK# signal is asserted, the Stop Grant state of the processor is entered 20 bus clocks after the response phase of the processor cores executes the HALT instruction, that the processor FSB frequency is changed...
Data Sheet
Page 88
... Any transition on the FSB). When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the Stop-Grant state will be asserted when the processor is out of the Extended HALT state or Extended Stop Grant state. While...state entered when the STPCLK# signal is a low-power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The processor will remain in the lower bus ratio and VID operating point of specification and may result in unapproved operation. Sleep ...
... Any transition on the FSB). When entering the low power state, the processor will first switch to the lower bus ratio and then transition to the Stop-Grant state will be asserted when the processor is out of the Extended HALT state or Extended Stop Grant state. While...state entered when the STPCLK# signal is a low-power state in which the processor maintains its context, maintains the phase-locked loop (PLL), and stops all internal clocks. The processor will remain in the lower bus ratio and VID operating point of specification and may result in unapproved operation. Sleep ...