Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Support and Manuals
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Programming Manual - Page 2
...
Intel® Virtualization Technology-enabled BIOS and VMM applications are referenced in development.
64-bit computing on your product order.
Intel reserves these features or instructions for conflicts or incompatibilities arising from :
Intel Corporation P.O. Processors will vary depending on Intel architecture requires a computer system with your distributor to specifications...
Programming Manual - Page 17
... stored in C_MSR_PMON_GLOBAL_CTL and the U-Box to be monitored by its respective data counter. The .en bit must also be enabled in the uncore global state registers. Table 2-6. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
2.2
U-Box Performance Monitoring
The U-Box serves as the system configuration controller for however...
Programming Manual - Page 22
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
2.3.3
C-BOX Performance Monitors
Table 2-9. C-Box Performance Monitoring MSRs
MSR Name
Acces s
MSR Addres
s
Size (bits
)
Description
CB7_CR_C_MSR_PMON_CTR_5
RW_R W
0xDFB 64 C-Box 7 PMON Counter 5
CB7_CR_C_MSR_PMON_EVT_SEL_5
RW_RO 0xDFA 64 C-Box 7 PMON Event Select 5
...
Programming Manual - Page 23
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
MSR Name
Acces s
MSR Addres
s
Size (bits
)
Description
CB5_CR_C_MSR_PMON_CTR_5
RW_R W
0xDBB 64 C-Box 5 PMON Counter 5
CB5_CR_C_MSR_PMON_EVT_SEL_5
RW_RO 0xDBA 64 C-Box 5 PMON Event Select 5
CB5_CR_C_MSR_PMON_CTR_4
RW_R W
0xDB9 64 C-Box 5 PMON Counter 4
CB5_CR_C_MSR_PMON_EVT_SEL_4
...
Programming Manual - Page 25
It is necessary to set the .ctr_en bit to enable monitoring.
The _GLOBAL_CTL register contains the bits used to 1 before the corresponding data register can collect events.
2-13 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
MSR Name
Acces s
MSR Addres
s
Size (bits
)
Description
CB4_CR_C_MSR_PMON_CTR_3
RW_R W
0xD37 64 C-Box 4 PMON...
Programming Manual - Page 57
..., must be cleared by setting the corresponding bit in the Intel Xeon Processor 7500 Series supports event monitoring through 4 48b wide counters (S_MSR_PMON_CTR/CTL{3:0}). INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
2.5
S-Box Performance Monitoring
2.5.1
Overview of 64 per cycle. Each of these bits are accumulated before they are...
Programming Manual - Page 63
...PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
Field ig addr
hnid
Table 2-35. Field Definitions
Bits
HW Reset
Val
Description
62:39 38:1
0
Read zero; If it is clear the it must match the corresponding address match bit in Section 2.5.5, "S-Box Events Ordered By Code". Associated with each mask bit that is set, the corresponding bit...which supports the...is 64 ...
Programming Manual - Page 85
... table specifies the port resources. For information on how to setup a monitoring session, refer to monitor (e.g.
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
2.6.1.3
R-Box Output Port
The R-Box output port acts as a virtual wire that allow a user to match packets serviced (packet is transferred from further downstream paths to on...
Programming Manual - Page 97
... 2-52, "R_MSR_PORT{7-0}_XBR_SET{2-1}_MASK Registers"). Shared b0001 - INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
To use by PMUs.
0x0 Read zero;
R_MSR_PORT{7-0}_XBR_SET{2-1}_MM_CFG Registers
Bits
HW Reset
Val
Description
63 62:22
21
20
19:16
15:8 7:0
0x0 Disable; Bit settings are mutually exclusive.
47:36 35:31 30...
Programming Manual - Page 99
...Ordered By Code
Table 2-54 summarizes the directly-measured R-Box events.
2-87 NOTE: Bits 71:16 of the R-Box's ports (NEW_PACKETS_RECV) , raw flit traffic (i.e.
A DRS message can be set ).
... valid.
0x1F00 Any Non Data Response completion message.
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
Table 2-53. The metric DRS....
Programming Manual - Page 110
... M-Box 1 PMON Global Overflow Status
MB1_CR_M_MSR_PERF_GLOBAL_CTL
RW_RW 0x0CE0 32 M-Box 1 PMON Global Control
MB0_CR_M_MSR_PMU_CNT_5 MB0_CR_M_MSR_PMU_CNT_CTL_5
RW_RW 0x0CBB 64 M-Box 0 PMON Counter 5 RW_RW 0x0CBA 64 M-Box 0 PMON Control 5
2-98 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
2.7.4
M-BOX Performance Monitors
Table 2-63.
Programming Manual - Page 111
INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
MSR Name
MB0_CR_M_MSR_PMU_CNT_4 MB0_CR_M_MSR_PMU_CNT_CTL_4 MB0_CR_M_MSR_PMU_CNT_3 MB0_CR_M_MSR_PMU_CNT_CTL_3 MB0_CR_M_MSR_PMU_CNT_2 MB0_CR_M_MSR_PMU_CNT_CTL_2 MB0_CR_M_MSR_PMU_CNT_1 MB0_CR_M_MSR_PMU_CNT_CTL_1 MB0_CR_M_MSR_PMU_CNT_0 MB0_CR_M_MSR_PMU_CNT_CTL_0
Access
MSR Address
Size (bits)
...
Programming Manual - Page 112
... Table 2-65.
M_MSR_PERF_GLOBAL_CTL Register Fields
Bits
HW Reset
Val
Description
5:0
0 Must be set to enable each MBOX 0 counter (bit 0 to enable ctr0, etc)
NOTE: U-Box enable and per counter enable must be set .
Table 2-66. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
Field ctr_en
Table 2-64. The main task of the...
Programming Manual - Page 120
..., the following triggers listed in the Intel SMI spec status frame description. See Table 2-81... NBDE event. If event select is set to 111 and this bit is set to match on . See Table 2-81...bits over all the Intel 7500 Scalable Memory Buffers is not a link-level CRC error).
0b000 Link level Intel SMI CRC error detected.
2-108 INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE...
Programming Manual - Page 137
... Fields
Field
fixed_en ig ctr_en
Bits
HW Reset
Val
Description
31 30:4
3:0
0 Enable the fixed counter
0 Read zero; The _GLOBAL_CTL register contains the bits used to fully enable the counter.
2-125 Table 2-95. To reset the overflow bits set in the W-Box. INTEL® XEON® PROCESSOR 7500 SERIES UNCORE PROGRAMMING GUIDE
UNCORE PERFORMANCE MONITORING
2.8.3
W-BOX Performance...
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