Product Specification
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... number, D33025. Product Certification Markings Description UL joint US/Canada Recognized Component mark. Includes Intel name and D101GGC model designation. Includes adjacent MIC certification number: CPU-D101GGC For information about MIC certification, go to European Union (EU) EMC directive (89/336/EEC) and Low Voltage directive (73/23/EEC). Mark FCC ...
... number, D33025. Product Certification Markings Description UL joint US/Canada Recognized Component mark. Includes Intel name and D101GGC model designation. Includes adjacent MIC certification number: CPU-D101GGC For information about MIC certification, go to European Union (EU) EMC directive (89/336/EEC) and Low Voltage directive (73/23/EEC). Mark FCC ...
Product Specification
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... (SMBIOS 63 3.5 Legacy USB Support...63 3.6 BIOS Updates ...64 3.7 Boot Options ...65 3.8 Adjusting Boot Speed 66 3.9 BIOS Security Features 67 3.1 Introduction The boards use an Intel BIOS that is set to put the Desktop Board in the Firmware Hub (FWH) and can be updated using a disk-based program. When the BIOS... test begins and before the operating system boot begins. 3 Overview of BIOS and a revision code. The BIOS Setup program is poweredup, the BIOS compares the CPU version and the microcode version in configure mode.
... (SMBIOS 63 3.5 Legacy USB Support...63 3.6 BIOS Updates ...64 3.7 Boot Options ...65 3.8 Adjusting Boot Speed 66 3.9 BIOS Security Features 67 3.1 Introduction The boards use an Intel BIOS that is set to put the Desktop Board in the Firmware Hub (FWH) and can be updated using a disk-based program. When the BIOS... test begins and before the operating system boot begins. 3 Overview of BIOS and a revision code. The BIOS Setup program is poweredup, the BIOS compares the CPU version and the microcode version in configure mode.
Product Specification
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...minute. 2. Initialize the APIC. 4. If no special interrupts are specified, all hardware interrupts are not identical. Initialize L2 cache and program CPU with proper cacheable range. 3. Load CMOS settings into C000:0. If CMOS checksum fails, use . On MP platform, adjust the cacheable ...2 Test 8259 functionality Initialize EISA slot Calculate total memory by OEM customers. Put information on screen display, including Award title, CPU type, and CPU speed. continued 71 Disable respective clock resource to smaller one in case the cacheable ranges between each 64K page. 1. Port ...
...minute. 2. Initialize the APIC. 4. If no special interrupts are specified, all hardware interrupts are not identical. Initialize L2 cache and program CPU with proper cacheable range. 3. Load CMOS settings into C000:0. If CMOS checksum fails, use . On MP platform, adjust the cacheable ...2 Test 8259 functionality Initialize EISA slot Calculate total memory by OEM customers. Put information on screen display, including Award title, CPU type, and CPU speed. continued 71 Disable respective clock resource to smaller one in case the cacheable ranges between each 64K page. 1. Port ...