Programmer Manual
Page 15
... 64-bit addressing for high-performance and cost effective Ethernet NICs (Network Interface Cards). A separate 4-wire Serial EEPROM port allows for an Ethernet PCI adapter to directly connect (via a Medium Independent Interface (MII) -based PHY and line transformer) to 2 KBytes. The AIC-6915 integrates all the functions necessary for downloading configuration information such as defined by the IEEE 802.3x specification. The AIC-6915 supports VLAN tagging...
... 64-bit addressing for high-performance and cost effective Ethernet NICs (Network Interface Cards). A separate 4-wire Serial EEPROM port allows for an Ethernet PCI adapter to directly connect (via a Medium Independent Interface (MII) -based PHY and line transformer) to 2 KBytes. The AIC-6915 integrates all the functions necessary for downloading configuration information such as defined by the IEEE 802.3x specification. The AIC-6915 supports VLAN tagging...
Programmer Manual
Page 16
... error handling. Transmit DMA Complete (Early Transmit) - AIC-6915 Ethernet LAN Controller Programmer's Manual Features General s Supports four general purpose I/Os that supports Category 3 UTP, Category 5 UTP, Type 1 STP and Fiber cables s IEEE 802.3.x compliant Flow Control mechanism s Supports Cisco proprietary VLAN ISL frame format s Supports IEEE 802.1q (VLAN) frame format s Supports PCI and OnNow power management s Supports OnNow wakeup function s Calculates TCP/IP checksum in transmit mode...
... error handling. Transmit DMA Complete (Early Transmit) - AIC-6915 Ethernet LAN Controller Programmer's Manual Features General s Supports four general purpose I/Os that supports Category 3 UTP, Category 5 UTP, Type 1 STP and Fiber cables s IEEE 802.3.x compliant Flow Control mechanism s Supports Cisco proprietary VLAN ISL frame format s Supports IEEE 802.1q (VLAN) frame format s Supports PCI and OnNow power management s Supports OnNow wakeup function s Calculates TCP/IP checksum in transmit mode...
Programmer Manual
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... ROM address space s Supports an external serial EEPROM for the first target access cycle. Memory Write And Invalidate s Supports PCI bus address and data parity generation and checking s Supports PCI PERR and SERR requirements s Supports 8-bit, 256-KByte, external Memory port for interface with external Boot ROM or devices/registers s Supports external Boot ROM access from configuration, I/O and memory address spaces s Supports PCI slave access to complete 1-4 AIC-6915 Ethernet LAN Controller Programmer's Manual -
... ROM address space s Supports an external serial EEPROM for the first target access cycle. Memory Write And Invalidate s Supports PCI bus address and data parity generation and checking s Supports PCI PERR and SERR requirements s Supports 8-bit, 256-KByte, external Memory port for interface with external Boot ROM or devices/registers s Supports external Boot ROM access from configuration, I/O and memory address spaces s Supports PCI slave access to complete 1-4 AIC-6915 Ethernet LAN Controller Programmer's Manual -
Programmer Manual
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... is a MAC control frame other than a pause frame as defined in a frame whose header was transferred. This field is a TCP or UDP packet, the checksum was a TCP frame 19 UdpFrame - AIC-6915 Ethernet LAN Controller Programmer's Manual Table 2-8. destination address matches one of the first buffer used . 2-8 If set , the completion descriptor is for the remaining data in the IEEE 802.3x specification. 13 ControlFrame...
... is a MAC control frame other than a pause frame as defined in a frame whose header was transferred. This field is a TCP or UDP packet, the checksum was a TCP frame 19 UdpFrame - AIC-6915 Ethernet LAN Controller Programmer's Manual Table 2-8. destination address matches one of the first buffer used . 2-8 If set , the completion descriptor is for the remaining data in the IEEE 802.3x specification. 13 ControlFrame...
Programmer Manual
Page 46
... use of proceeding with the RMA (Received Master Abort in the BAC module. Intervention by the software driver is not asserted by the software driver is serviced. The software driver can be aligned on a 32-bit boundary. The PCI ...problem. Intervention by the selected target for Interrupt Acknowledge, Special Cycle, I/O space, or Configuration space. In normal operation mode, the AIC-6915 continues the DMA transfer even if a parity error is set. The PCI master detects and reports parity errors. AIC-6915 Ethernet LAN Controller Programmer's Manual PCI Master Module The PCI...
... use of proceeding with the RMA (Received Master Abort in the BAC module. Intervention by the software driver is not asserted by the software driver is serviced. The software driver can be aligned on a 32-bit boundary. The PCI ...problem. Intervention by the selected target for Interrupt Acknowledge, Special Cycle, I/O space, or Configuration space. In normal operation mode, the AIC-6915 continues the DMA transfer even if a parity error is set. The PCI master detects and reports parity errors. AIC-6915 Ethernet LAN Controller Programmer's Manual PCI Master Module The PCI...
Programmer Manual
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... Ethernet LAN Controller Programmer's Manual Expansion ROM Address Space When in target mode, the AIC-6915 allows access to an 8-bit ROM/EEPROM (connected to complete the decode. Usually this kind of AD[31:00] (for which the PAR is invalid). The AIC-6915 only supports the linear address increment mode. As a target device, the AIC-6915 allows accesses to indicate different memory address...
... Ethernet LAN Controller Programmer's Manual Expansion ROM Address Space When in target mode, the AIC-6915 allows access to an 8-bit ROM/EEPROM (connected to complete the decode. Usually this kind of AD[31:00] (for which the PAR is invalid). The AIC-6915 only supports the linear address increment mode. As a target device, the AIC-6915 allows accesses to indicate different memory address...
Programmer Manual
Page 58
... Mode When the chip is functioning in power down mode, the GFP is on a byte boundary. Instead the input STARTOFFRAME is presented as outputs also. When the GFP is a bit in the sum. The GFP then decrements the LC by the number given by an address defined... the counters 3 least significant bits and activates the accelerator only when they are available as 0 x 0 to signal the beginning of frame data are included in the instruction. AIC-6915 Ethernet LAN Controller Programmer's Manual s LC= 0, 1 or 2, and EXCONCLOCK is set, or s Read/Write instruction is executed and the Input IOREADY...
... Mode When the chip is functioning in power down mode, the GFP is on a byte boundary. Instead the input STARTOFFRAME is presented as outputs also. When the GFP is a bit in the sum. The GFP then decrements the LC by the number given by an address defined... the counters 3 least significant bits and activates the accelerator only when they are available as 0 x 0 to signal the beginning of frame data are included in the instruction. AIC-6915 Ethernet LAN Controller Programmer's Manual s LC= 0, 1 or 2, and EXCONCLOCK is set, or s Read/Write instruction is executed and the Input IOREADY...
Programmer Manual
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... as the offset byte address from the start of the memory space dedicated for configuration, control, and retrieval of the register. AIC-6915 Ethernet LAN Controller Programmer's Manual Terminology Throughout this chapter, data values are defined as follows: s Byte = 8 bits s Halfword = 16 bits s Word = 32 bits s Doubleword = 64 bits AIC-6915 Internal Registers These registers are used by the software driver for internal registers...
... as the offset byte address from the start of the memory space dedicated for configuration, control, and retrieval of the register. AIC-6915 Ethernet LAN Controller Programmer's Manual Terminology Throughout this chapter, data values are defined as follows: s Byte = 8 bits s Halfword = 16 bits s Word = 32 bits s Doubleword = 64 bits AIC-6915 Internal Registers These registers are used by the software driver for internal registers...
Programmer Manual
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... time, the BR_A1 input is 6915h. The CCIS (Configuration Card Information Structure) and MAC address are no default values for these registers. PCI VendorID Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 00h - 01h Bit(s) 15:0 Table 7-3. PCI Device ID Register Bit(s) rw Reset Value Description/Function 15:0 r 6915h DeviceID[15:0]: The PCI Device Identifier registers contain product information for the AIC...
... time, the BR_A1 input is 6915h. The CCIS (Configuration Card Information Structure) and MAC address are no default values for these registers. PCI VendorID Register Type: R Internal Registers Subgroup: PCI Configuration Header Byte Address: 00h - 01h Bit(s) 15:0 Table 7-3. PCI Device ID Register Bit(s) rw Reset Value Description/Function 15:0 r 6915h DeviceID[15:0]: The PCI Device Identifier registers contain product information for the AIC...
Programmer Manual
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... 20 19 Table 7-31. r 0 Reserved: Always read as an active PCI master, measured from the D0, D1 and D2 power states. AIC-6915 Ethernet LAN Controller Programmer's Manual PCIMonitor2 Register Type: R Internal Registers Subgroup: PCI Functional Registers Byte Address: 4Ch - 4Fh Table 7-30. r 0 Auxiliary Power Source: This bit is only meaningful when PME_ is asserted when detecting a 'wake-up' frame or Link Fail.
... 20 19 Table 7-31. r 0 Reserved: Always read as an active PCI master, measured from the D0, D1 and D2 power states. AIC-6915 Ethernet LAN Controller Programmer's Manual PCIMonitor2 Register Type: R Internal Registers Subgroup: PCI Functional Registers Byte Address: 4Ch - 4Fh Table 7-30. r 0 Auxiliary Power Source: This bit is only meaningful when PME_ is asserted when detecting a 'wake-up' frame or Link Fail.
Programmer Manual
Page 95
...' - D3 Reset Value: In CardBus mode, (when the EPROM A0 pin is not implemented. Otherwise, it consumes. r 0 Reserved: Always read as 0. r/w 0 PmeEn: This bit enables the function to the location of next item in revision 1.0 of the 'PCI Bus Power Management Interface Specification'. 15:8 r 00h NextItemPtr: This field provides an offset into the function's PCI configuration space pointing...
...' - D3 Reset Value: In CardBus mode, (when the EPROM A0 pin is not implemented. Otherwise, it consumes. r 0 Reserved: Always read as 0. r/w 0 PmeEn: This bit enables the function to the location of next item in revision 1.0 of the 'PCI Bus Power Management Interface Specification'. 15:8 r 00h NextItemPtr: This field provides an offset into the function's PCI configuration space pointing...
Programmer Manual
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... Description/Function 31:4 r 3 r 0 Reserved: Always read as a Link Fail indicator. When the command is completed the bit is finished. PME_ is set up not to issue a 'Write Disable' command. Serial EEPROMControlStatus Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 60h - 63h Table 7-34. AIC-6915 Ethernet LAN Controller Programmer's Manual PME Event Register Type: R/W Internal Registers Subgroup...
... Description/Function 31:4 r 3 r 0 Reserved: Always read as a Link Fail indicator. When the command is completed the bit is finished. PME_ is set up not to issue a 'Write Disable' command. Serial EEPROMControlStatus Register Type: R/W Internal Registers Subgroup: PCI Functional Registers Byte Address: 60h - 63h Table 7-34. AIC-6915 Ethernet LAN Controller Programmer's Manual PME Event Register Type: R/W Internal Registers Subgroup...
Programmer Manual
Page 103
... a '1'. 0 SoftInt: This bit is configured to the Set Soft Interrupt bit in the INTERRUPTEN register is set when the software driver writes a '1' to be an input and set an interrupt when its terminal Count of the interrupt status bits in PCIStatus register is set and the corresponding enable bit in PCIConfig register is below a programmable threshold. InterruptStatus Register Reset Bit(s) rw Value Description...
... a '1'. 0 SoftInt: This bit is configured to the Set Soft Interrupt bit in the INTERRUPTEN register is set when the software driver writes a '1' to be an input and set an interrupt when its terminal Count of the interrupt status bits in PCIStatus register is set and the corresponding enable bit in PCIConfig register is below a programmable threshold. InterruptStatus Register Reset Bit(s) rw Value Description...
Programmer Manual
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... Ethernet LAN Controller Programmer's Manual Table 7-62. The programmable threshold in bytes is used for the producer to be an integral number of buffer (in bytes) in Prefetch mode. D7h Note: Many of receive DMA requests. RxDescQueue1Ctrl Register Reset Bit(s) rw Value Description/Function 31:16 r/w 15 r/w x RxQ1BufferLength[15:0]: Indicates the length of 4-byte words. 0 RxPrefetchDescriptorsMode: Setting this bit is set...
... Ethernet LAN Controller Programmer's Manual Table 7-62. The programmable threshold in bytes is used for the producer to be an integral number of buffer (in bytes) in Prefetch mode. D7h Note: Many of receive DMA requests. RxDescQueue1Ctrl Register Reset Bit(s) rw Value Description/Function 31:16 r/w 15 r/w x RxQ1BufferLength[15:0]: Indicates the length of 4-byte words. 0 RxPrefetchDescriptorsMode: Setting this bit is set...
Programmer Manual
Page 143
... any configuration register state. 14 r/w 0 MIILoopBack: All transmit MII signals, including data and control, are connected to 32 bytes of an Ethernet packet and compares it with a bad preamble. Clearing the bit causes the MAC to detect up to the transmit side and may stop or start the transmit operation. 0 Preamble Detect Count: Setting this bit is set , 'pause' frames (one...
... any configuration register state. 14 r/w 0 MIILoopBack: All transmit MII signals, including data and control, are connected to 32 bytes of an Ethernet packet and compares it with a bad preamble. Clearing the bit causes the MAC to detect up to the transmit side and may stop or start the transmit operation. 0 Preamble Detect Count: Setting this bit is set , 'pause' frames (one...
Programmer Manual
Page 144
... process called 'truncated binary exponential backoff'. MacConfig1 Register (Continued) Reset Bit(s) rw Value Description/Function 5 r/w 0 NoBackoff: Controls the backoff algorithm after a collision. The retransmission is invoked every time a collision occurs during a transmit operation. AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-91. The number of slot times of delay before the nth retransmission attempt is chosen as a uniformly...
... process called 'truncated binary exponential backoff'. MacConfig1 Register (Continued) Reset Bit(s) rw Value Description/Function 5 r/w 0 NoBackoff: Controls the backoff algorithm after a collision. The retransmission is invoked every time a collision occurs during a transmit operation. AIC-6915 Ethernet LAN Controller Programmer's Manual Table 7-91. The number of slot times of delay before the nth retransmission attempt is chosen as a uniformly...
Programmer Manual
Page 163
... reset. The reset sequence is available. Operating system-specific calls may be used to each operating system and will require that the controller be covered here in the DDK is through PCI configuration cycles. These are not required. With the exception of finding the card is memory-mapped. Sample Driver Basic Register Initialization and Reset Sequence The first step in the PCI configuration...
... reset. The reset sequence is available. Operating system-specific calls may be used to each operating system and will require that the controller be covered here in the DDK is through PCI configuration cycles. These are not required. With the exception of finding the card is memory-mapped. Sample Driver Basic Register Initialization and Reset Sequence The first step in the PCI configuration...
Programmer Manual
Page 164
... desired settings. The MACSOFTRST bit must be initialized to enable memory and/or I/O register access, to enable bus master mode, to enable Memory Write and Invalidate, and to the Seeq data sheet for a reset operation. 3 PHY Reset: PHY initialization in this register is set . This is referred to enable system error response. RxDmaEn = 1: Enable receive DMA. - AIC-6915 Ethernet LAN Controller Programmer's Manual 1 PCI COMMAND...
... desired settings. The MACSOFTRST bit must be initialized to enable memory and/or I/O register access, to enable bus master mode, to enable Memory Write and Invalidate, and to the Seeq data sheet for a reset operation. 3 PHY Reset: PHY initialization in this register is set . This is referred to enable system error response. RxDmaEn = 1: Enable receive DMA. - AIC-6915 Ethernet LAN Controller Programmer's Manual 1 PCI COMMAND...
Programmer Manual
Page 169
... option is set by the driver. These registers and the fields which require initialization are selected through the BUFFERQUEUE bit in the STATUS1 field in the Perfect Addressing table. Register bits which must be modified for the case of 32-bit addressing. Use of two completion queues does not dictate the use a producer-consumer model to implement the polling model instead of...
... option is set by the driver. These registers and the fields which require initialization are selected through the BUFFERQUEUE bit in the STATUS1 field in the Perfect Addressing table. Register bits which must be modified for the case of 32-bit addressing. Use of two completion queues does not dictate the use a producer-consumer model to implement the polling model instead of...
Programmer Manual
Page 173
....RxQ1BufferLength = AIC6915_SIZE_OF_RX_BUFFERS; // Write the value to zero AIC6915_WRITE_REG(Adapter->RegisterBaseVa->CompletionQueue1ConsumerIndex, 0); use default value for RxDescQueue2Ctrl // Set up the Receive Buffer Descriptor Queue 8-13 This entry must be set for polling model. // It's important only in producer-consumer model. Sample Driver // assign the base address of the completion queue (high 24 bits) RxCompletionQueue1CtrlValue.RxCompletionQ1BaseAddress = NdisGetPhysicalAddressLow(RxCompletionQ) >> 8; // Write the value to...
....RxQ1BufferLength = AIC6915_SIZE_OF_RX_BUFFERS; // Write the value to zero AIC6915_WRITE_REG(Adapter->RegisterBaseVa->CompletionQueue1ConsumerIndex, 0); use default value for RxDescQueue2Ctrl // Set up the Receive Buffer Descriptor Queue 8-13 This entry must be set for polling model. // It's important only in producer-consumer model. Sample Driver // assign the base address of the completion queue (high 24 bits) RxCompletionQueue1CtrlValue.RxCompletionQ1BaseAddress = NdisGetPhysicalAddressLow(RxCompletionQ) >> 8; // Write the value to...