Data Sheet
Page 2
... a processor with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for more information, see http://www.intel.com/technology/security/ ‡ Not all operating systems. Please check with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). Intel, Pentium, Intel Core, Intel SpeedStep, and the Intel logo...
... a processor with a processor, chipset, BIOS, operating system, device drivers, and applications enabled for more information, see http://www.intel.com/technology/security/ ‡ Not all operating systems. Please check with Intel® Virtualization Technology, an Intel TXT-enabled processor, chipset, BIOS, Authenticated Code Modules and an Intel TXT-compatible measured launched environment (MLE). Intel, Pentium, Intel Core, Intel SpeedStep, and the Intel logo...
Data Sheet
Page 30
... are not required as these are determined by the input buffers by a voltage divider of the GTL+ output driver. 4. Valid high and low levels are integrated into the processor silicon. Unless otherwise noted, all processor frequencies. 2. PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes1 Vin Input Voltage Range Vhysteresis...
... are not required as these are determined by the input buffers by a voltage divider of the GTL+ output driver. 4. Valid high and low levels are integrated into the processor silicon. Unless otherwise noted, all processor frequencies. 2. PECI DC Electrical Limits Symbol Definition and Conditions Min Max Units Notes1 Vin Input Voltage Range Vhysteresis...
Data Sheet
Page 66
... Listing and Signal Descriptions Table 4-3. The data driver asserts DRDY# to indicate that an in-target...63:0]# are activated when the data on all processor FSB agents. 66 Datasheet D[63:0]# are latched off the falling edge of the D[63:0]# signals.The DBI[3:0]# signals are quad-pumped signals and will, thus, be driven ...DBI# signal is active, the corresponding data group is de-asserted. Signal Description (Sheet 3 of the data signals. D[63:0]# Input/ Output Quad-Pumped Signal Groups Data Group DSTBN#/ DSTBP# DBI# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]#...
... Listing and Signal Descriptions Table 4-3. The data driver asserts DRDY# to indicate that an in-target...63:0]# are activated when the data on all processor FSB agents. 66 Datasheet D[63:0]# are latched off the falling edge of the D[63:0]# signals.The DBI[3:0]# signals are quad-pumped signals and will, thus, be driven ...DBI# signal is active, the corresponding data group is de-asserted. Signal Description (Sheet 3 of the data signals. D[63:0]# Input/ Output Quad-Pumped Signal Groups Data Group DSTBN#/ DSTBP# DBI# D[15:0]# 0 0 D[31:16]# 1 1 D[47:32]# 2 2 D[63:48]#...
Data Sheet
Page 67
...FCx Other Other FC0/BOOTSELECT is asserted by the processor. When this land is asserted by the data driver on each data transfer, indicating valid data on all platforms. NOTE:Some processors may not be available on the Intel NetBurst® microarchitecture should be available on the ...data bus. Datasheet 67 Use of all processor FSB agents. To return to latch...
...FCx Other Other FC0/BOOTSELECT is asserted by the processor. When this land is asserted by the data driver on each data transfer, indicating valid data on all platforms. NOTE:Some processors may not be available on the Intel NetBurst® microarchitecture should be available on the ...data bus. Datasheet 67 Use of all processor FSB agents. To return to latch...
Data Sheet
Page 82
... not be latched and kept pending until the processor resumes operation at the lower voltage reduces the power consumption of this condition, the core-frequency-to execute instructions during the voltage transition....drivers, or interrupt handling routines. The second operating point consists of 5 μs). During the frequency transition, the processor is unable to adjust its normal operating frequency. Under this ordering. 82 Datasheet The processor continues to -FSB multiple utilized by reducing the power consumption within the processor. Thermal Monitor 2 The processor...
... not be latched and kept pending until the processor resumes operation at the lower voltage reduces the power consumption of this condition, the core-frequency-to execute instructions during the voltage transition....drivers, or interrupt handling routines. The second operating point consists of 5 μs). During the frequency transition, the processor is unable to adjust its normal operating frequency. Under this ordering. 82 Datasheet The processor continues to -FSB multiple utilized by reducing the power consumption within the processor. Thermal Monitor 2 The processor...