Intel E6320 - Core 2 Duo Dual-Core Processor Support and Manuals
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Battlefield 3 on Core 2 Duo E6320 Underclocked to 700Mhz
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Duration: 15:40
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My second PC E6320 7950GT 2GB DDR2
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Intel Core 2 Duo E6320 1.86GHz @ 3,84 GHz (1,44V und Kokü @ -47°C)
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Duration: 2:27
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e6320 overclocked on Intel Dg41rq
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Popular Intel E6320 Manual Pages
Specification Update - Page 2
..., BIOS, and virtual machine monitor (VMM). Consult your PC manufacturer. Performance varies depending on Intel® Core™ i5750. For Enhanced Intel SpeedStep® Technology, see the Processor Spec Finder at any time, without notice. Consult your Intel representative for more information. All Rights Reserved.
2
Specification Update Contact your local Intel sales office or...
Specification Update - Page 14
... Redirection
Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior
IA32_MC5_CTL2 is Not Cleared by a Warm Reset
Performance Monitor Counters May Produce Incorrect Results
The Corrected Error Count Overflow Bit in IA32_ MC0_STATUS is Not Updated After a UC Error is Logged Spurious Intel® VT-d Interrupts May Occur When the PFO Bit is Set
Processor May...
Specification Update - Page 20
... steppings affected, see the Summary Tables of Changes.
20
Specification Update Workaround: As recommended in the IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS/POP SS in incorrect signaling of the following instruction should be logged in a system hang causing an Internal Timer Error (MCACOD = 0x0400h) to be executed atomically.
The corresponding...
Specification Update - Page 24
... has not occurred.
3.
Page Fault (#PF)). Workaround: None identified. Problem:
Faulting MMX Instruction May Incorrectly Update x87 FPU Tag Word
Under a specific set , a PEBS should not be the first MMX instruction to a 0x0000 value when it should be Preempted
Problem:
When the processor encounters an instruction that uses an index register (this erratum, if:
1. This erratum...
Specification Update - Page 26
... MCi_Status register. Workaround: Do not execute MONITOR or CLFLUSH instructions on a Single Instance of an exception/ interrupt.
LBR, BTS, BTM May Report a Wrong Address when an Exception/ Interrupt Occurs in the event of a DTLB Error
Problem:
A single Data Translation Look Aside Buffer (DTLB) error can incorrectly set the
Overflow (bit [62]) in the MCi_Status register...
Specification Update - Page 29
... erratum may cause a #TS (invalid TSS exception) instead of a #GP Fault
Problem:
A jump to 1, a VM exit with any instruction
if there is configured for NMI virtualization should generally be unaffected, as the erratum causes at most a one instruction following the counter overflow.
Specification Update
29 BJ29. Due to this erratum with exit reason "NMI window" should...
Specification Update - Page 30
..., according to
the PCIe specification, should not issue unsupported accesses. Implication: The processor response to an unsupported PCIe access may not fully comply to the same byte count as critical errors. BJ34. Implication: Legacy malformed PCIe transactions may treat such messages as a BTM on the system bus will incorrectly update the LBR (Last Branch...
Specification Update - Page 33
...Problem:
The "From" address associated with vex.vvvv !=1111b results in the Queued Invalidation descriptors of Changes. Specification Update... affected, see the Summary Tables of Intel VT-d (Virtualization Technology for the first branch after a...Setting Reserved Bits of Intel® VT-d Queued Invalidation Descriptors
Problem:
Reserved bits in the same behavior as zero while the processor...
Specification Update - Page 34
... is that the logical processor will set the vvvv field of VMREAD or VMWRITE should avoid accessing unsupported fields in VMCS
The Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2B states that execution of the VEX prefix to properly report an error. Workaround: None identified. BJ44. Problem:
VMREAD/VMWRITE Instruction May Not Fail...
Specification Update - Page 39
... in unexpected behavior if the XSAVE instruction writes to 25 degrees higher than intended.
BJ61.
Intel has not observed this erratum with any system failures due to a delay in the Intel® 64 and IA-32 Architectures Optimization Reference Manual.
C-state Exit Latencies May be Higher Than Expected
Problem:
Core C-state exit can be over twice...
Specification Update - Page 40
...BJ62.
Intel® VT-d Interrupt Remapping Will Not Report a Fault if Interrupt Index Exceeds FFFFH
Problem:
With Intel VT-d (Virtualization Technology for Directed I/O) interrupt remapping, if subhandle valid (bit 3) is the L2 Cache. Interrupts blocked in the address of 01 is set in this way produce a remapping fault with a cache error type of Changes.
40
Specification Update
Specification Update - Page 45
... up the processor graphics logic in display corruption.
Sugar Bay and Bromolow-WS
Status:
For the steppings affected, see the Summary Tables of Changes.
Workaround: A graphics driver workaround has been identified and may be implemented as a workaround for this erratum.
BJ84.
PCI Express* Differential Peak-Peak Tx Voltage Swing May Violate the Specification
Problem:
Under...
Specification Update - Page 54
..., see the Summary Tables of Changes.
VEX.L is Not Ignored with VCVT*2SI Instructions
Problem:
The VEX.L bit should be
incorrect, even though MCi_Status.ADDRV (bit 63) is set to this error should be logged in MCi_ADDR may be invoked as part of VM entry.
Due to this erratum applies only to executions outside 64...
Specification Update - Page 56
... not observed this erratum with any commercially available software. Specific Graphics Blitter Instructions May Result in Unpredictable Graphics Controller Behavior
Problem:
Specific source-copy blitter instructions in Intel® HD Graphics 2000 and 3000 Processor may be Lost
Problem:
A debug exception occurring at the time GETSEC commenced execution.
VM Exits Due to GETSEC...
Specification Update - Page 60
... Manual A-M • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2B: Instruction Set Reference Manual N-Z • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B: System Programming Guide
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60
Specification Update
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