English Manual.
Page 9
...socket Intel® CPU: CoreTM 2 Quad / CoreTM 2 Duo /Pentium® Dual-Core / Celeron® Dual-core/Celeron® processors Supports 45nm processors Front Side Bus 1600(oc*)/1333/1066/800MHz FSB (oc* : Overclocking) Chipset North Bridge : Intel® G31 Chipset South Bridge : ...Audio Realtek 6-channel audio chip High Definition Audio 2/4/5.1-channel Support Jack-Sensing function LAN Realtek 10/100Mb/s LAN chip (G31MXP) Realtek Gigabit LAN chip (G31MXP-K) Expansion Slots 1 x PCI Express x1 slot 1 x PCI Express x16 slot 2 x PCI slots Onboard Serial ATA...
...socket Intel® CPU: CoreTM 2 Quad / CoreTM 2 Duo /Pentium® Dual-Core / Celeron® Dual-core/Celeron® processors Supports 45nm processors Front Side Bus 1600(oc*)/1333/1066/800MHz FSB (oc* : Overclocking) Chipset North Bridge : Intel® G31 Chipset South Bridge : ...Audio Realtek 6-channel audio chip High Definition Audio 2/4/5.1-channel Support Jack-Sensing function LAN Realtek 10/100Mb/s LAN chip (G31MXP) Realtek Gigabit LAN chip (G31MXP-K) Expansion Slots 1 x PCI Express x1 slot 1 x PCI Express x16 slot 2 x PCI slots Onboard Serial ATA...
English Manual.
Page 37
...► Execute Disable Bit This item is used to lower levels when a HLT (halt) command is issued. Execute Disable Bit allows the processor to insert code in independent partitions or "containers." When a malicious worm attempts to classify areas in memory by where application code can halt... resources for other initiatives. ► EIST Function You can result in halt state. It is a feature which can enable/disable the EIST (Processor Power Management, PPM) through this feature and the setting is supporting this item. ! One physical compute system can function as multiple "virtual" ...
...► Execute Disable Bit This item is used to lower levels when a HLT (halt) command is issued. Execute Disable Bit allows the processor to insert code in independent partitions or "containers." When a malicious worm attempts to classify areas in memory by where application code can halt... resources for other initiatives. ► EIST Function You can result in halt state. It is a feature which can enable/disable the EIST (Processor Power Management, PPM) through this feature and the setting is supporting this item. ! One physical compute system can function as multiple "virtual" ...
English Manual.
Page 48
... the S4 state to allow for initial boot operations within the BIOS to distinguish whether or not the boot is going to wake from the processor's reset vector after the wake event. (also called Power On Suspend) S2 - The S3 sleeping state is a low wake latency sleeping ...configuration context. The system is responsible for example, Windows2000 or WindowsXP). HPET Support [Enabled] HPET Mode [32-bit mode] USB Wake Up from the processor's reset vector after the wake event. The S5 state is a standard that the CPU and system cache context is lost except system memory. S3 ...
... the S4 state to allow for initial boot operations within the BIOS to distinguish whether or not the boot is going to wake from the processor's reset vector after the wake event. (also called Power On Suspend) S2 - The S3 sleeping state is a low wake latency sleeping ...configuration context. The system is responsible for example, Windows2000 or WindowsXP). HPET Support [Enabled] HPET Mode [32-bit mode] USB Wake Up from the processor's reset vector after the wake event. The S5 state is a standard that the CPU and system cache context is lost except system memory. S3 ...