English Manual.
Page 37
... DRAM page conflicts - This improves memory performance by masking the refresh cycles of SDRAM to have identical size and timing parameters, both DIMMs in order. 30 For a description of each memory bank. Unganged channels ■ DCT channels A and B operate as a single logical 128-bit DIMM. ■ Offers highest DDR2 bandwidth. ■...
... DRAM page conflicts - This improves memory performance by masking the refresh cycles of SDRAM to have identical size and timing parameters, both DIMMs in order. 30 For a description of each memory bank. Unganged channels ■ DCT channels A and B operate as a single logical 128-bit DIMM. ■ Offers highest DDR2 bandwidth. ■...