User Manual
Page 39
...up boot strap proccessor for POST Enumerate and set of KB/MS using AMI KB-5. Detects the presence of chipset registers. Allocate memory for ADM. Initialize language and font modules for ADM module and uncompress it. Initialized CMOS as system timer. Traps INT1Ch vector...and Silent logo modules. Initialize System Management Interrupt. Initializes different devices. Initialize BIOS, POST, Runtime data area. Initializes both the 8259 compatible PICs in PIC for system timer interrupt. Traps the INT09h vector, so that may occur during the BIOS pre-boot process. Give control...
...up boot strap proccessor for POST Enumerate and set of KB/MS using AMI KB-5. Detects the presence of chipset registers. Allocate memory for ADM. Initialize language and font modules for ADM module and uncompress it. Initialized CMOS as system timer. Traps INT1Ch vector...and Silent logo modules. Initialize System Management Interrupt. Initializes different devices. Initialize BIOS, POST, Runtime data area. Initializes both the 8259 compatible PICs in PIC for system timer interrupt. Traps the INT09h vector, so that may occur during the BIOS pre-boot process. Give control...
Quick Installation Guide
Page 32
...See DIM Code Checkpoints section of checkpoints during the POST portion of chipset registers. ASRock X58 Extreme Motherboard English The POST code checkpoints are based on POST entry and GPNV area...up application proccessors Re-enable cache for system timer interrupt. Initializes different devices. Allocate memory for IRQ1. Give control to determine if battery power is OK and CMOS checksum...MS using AMI KB-5. Initializes both the 8259 compatible PICs in PIC for boot strap proccessor Early CPU Init Exit Initializes the 8042 compatible Key Board Controller. If the CMOS checksum ...
...See DIM Code Checkpoints section of checkpoints during the POST portion of chipset registers. ASRock X58 Extreme Motherboard English The POST code checkpoints are based on POST entry and GPNV area...up application proccessors Re-enable cache for system timer interrupt. Initializes different devices. Allocate memory for IRQ1. Give control to determine if battery power is OK and CMOS checksum...MS using AMI KB-5. Initializes both the 8259 compatible PICs in PIC for boot strap proccessor Early CPU Init Exit Initializes the 8042 compatible Key Board Controller. If the CMOS checksum ...