Intel X5472 - Cpu Xeon Quad Core 3.00Ghz Fsb1600Mhz 12M Lga771 Tray Support and Manuals
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Data Sheet - Page 9
... systems and applications written to the L2 cache before an L1 cache requests occurs, resulting in conjunction with IA-32 software. In addition, the Quad-Core Intel® Xeon® Processor 5400 Series supports the Execute Disable Bit functionality. When used in reduced effective bus latency and improved performance. SSE3 instructions provide highly efficient double-precision floating...
Data Sheet - Page 13
...® 64 and IA-32 Architectures Software Developer's Manual, Volume 3B
Intel® 64 and IA-32 Intel® Architectures Optimization Reference Manual
Intel® 64 and IA-32 Intel® Architectures Software Developer's Manual Documentation Changes
Quad-Core Intel® Xeon® Processor 5400 Series Specification Update
Document Number1
241618 253665 253666 253667 253668 253669 248966...
Data Sheet - Page 37
.... Please refer to processor I/O Buffer Models for VCC
overshoot specifications. 2. VIH and ...guide for processor VID information. 3. Quad-Core Intel® Xeon® Processor 5400 Series Electrical Specifications
Figure 2-10. Table 2-15. Measured at the VCC_DIE_SENSE and VSS_DIE_SENSE
lands and the VCC_DIE_SENSE2 and VSS_DIE_SENSE2 lands. Quad-Core Intel® Xeon® Processor...
Data Sheet - Page 74
...) is asserted by the data driver on each data
3
transfer, indicating valid data on the data bus.
When STPCLK# is qualified by the platform to cause the Quad-Core Intel® Xeon® Processor 5400 Series to activate the Thermal Control Circuit (TCC). The assertion of
FERR#/PBE# indicates that the
processor should be returned to indicate...
Data Sheet - Page 104
Boxed Processor Specifications
Figure 8-1. Boxed Quad-Core Intel® Xeon® Processor 5400 Series 2U Passive Heat Sink
104 Boxed Quad-Core Intel® Xeon® Processor 5400 Series 1U Passive/3U+ Active Combination Heat Sink (With Removable Fan)
Figure 8-2.
Specification Update - Page 13
... PS bit is set to "1" in a PML4E or PDPTE
X
No Fix Not-Present Page Faults May Set the RSVD Flag in the Error Code
X
No Fix VM Exits Due to "NMI-Window Exiting" May Be Delayed by One Instruction
X
No Fix A 64-bit Register IP-relative Instruction May Return Unexpected Results
13
Intel® Xeon® Processor 5400 Series
Specification Update
Specification Update - Page 16
...Intel® Xeon® Processor 5400 Series Identification Information (Sheet 1 of 2)
S-Spec
Processor Number
Core Stepping
CPUID1
Core Freq (GHz)
SLANZ SLANP SLASA SLASB SLANR SLANQ SLANS SLANT SLANU SLANV SLANW SLAP2 SLAP5 SLAP4 SLARP SLBBD SLBBG SLBBF SLBBB SLBBA
X5482 X5460 X5472...1333 1600 1333
L2 Cache
Size (MB)...Intel® Xeon® Processor 5400 Series
16
Specification Update
Specification Update - Page 17
...Intel® Xeon® Processor 5400 Series Identification Information (Sheet 2 of 2)
Processor
Core
S-Spec Number Stepping
CPUID1
Core Freq (GHz)
Data Bus Freq (MHz)
L2 Cache
...do support this technology.
17
Intel® Xeon® Processor 5400 Series
Specification Update E5405 does not support Intel SpeedStep® Technology. PPS Samples.
2. Table 1. Processors in the QDF/S-Spec ...
Specification Update - Page 21
.... No commercial operating system is a rare condition that access a busy TSS may result in Pentium 4, Intel Xeon, and P6 Family
21
Intel® Xeon® Processor 5400 Series
Specification Update
Intel has not observed this erratum. Workaround: This non-synchronization can be impacted by STI instruction. Status:
For the steppings affected, see the Summary Tables of a #GP fault.
Specification Update - Page 24
... HLT or MWAIT events, are also not counted:
a) RSM from an SMI during an MWAIT instruction. If the ISR does
Intel® Xeon® Processor 5400 Series
24
Specification Update
Status:
For the steppings affected, see the Summary Tables of Changes.
AX24. Intel has not observed this behavior in commercially available software. An interrupt may miscount retired...
Specification Update - Page 28
... unit and lack of Changes. This event is a Non-Integer Core-to IA32_
FIXED_CTR2.
Intel® Xeon® Processor 5400 Series
28
Specification Update
Implication: Due to -bus ratio enables additional operating frequencies.
AX39.
AX37. Non-integer core-to this erratum occurs in the IFU, the processor may cause the system to hang or to report a machine check...
Specification Update - Page 33
... of the IA32_MC1_CTL MSR enable bit.
Status:
For the steppings affected, see the Summary Tables of Changes. Specifically, information about the software interrupt
33
Intel® Xeon® Processor 5400 Series
Specification Update Error Enabled) is followed by this instruction is supposed to this erratum with MOV [r/e]SP, [r/e]BP will avoid the failure
since the MOV SS/POP...
Specification Update - Page 39
... by One Instruction
Problem:
If VM entry is ignored and no page fault will occur due to its being set to 1, a page fault should occur after execution of one additional instruction.
Not-Present Page Faults May Set the RSVD Flag in an unexpected page fault or unpredictable system behavior.
39
Intel® Xeon® Processor 5400 Series
Specification Update
VM...
Mechanical Design Guidelines - Page 32
... permanent damage to 80% of the TDP limit for Quad-Core Intel® Xeon® Processor X5400 Series with 120W TDP and 90% of meeting the thermal specification when local ambient temperature (TLA) is capable of the TDP limit for the Quad-Core Intel® Xeon® Processor X5482 with 80W TDP. The Intel 2U CEK is maintained at or below this Tcase level...
Mechanical Design Guidelines - Page 41
... support and stiffening on package/socket loading specifications.
Quad-Core Intel® Xeon® Processor 5400...error associated with the reference mechanical components:
• Requirement 1: Heatsink assembly must stay within this document, and should refer to the Quad-Core Intel® Xeon® Processor 5400 Series Datasheet and LGA771 Socket Mechanical Design Guide for specific...
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