Design Guide
Page 14
... use of AGP 4X, the Intel® 820 chipset delivers the data throughput necessary to take advantage of Intel chipsets. The addition of an appropriate LAN device, Intel® 820 chipset also supports Wake on , Stop Grant, Suspend to RAM, Suspend to Disk, and Soft...that was used for remote administration and troubleshooting. A new chipset component interconnect, the hub interface, is the third generation desktop chipset designed for Intel's SC242 architecture and the first chipset to main memory. This removes many of the conflicts experienced when installing hardware and ...
... use of AGP 4X, the Intel® 820 chipset delivers the data throughput necessary to take advantage of Intel chipsets. The addition of an appropriate LAN device, Intel® 820 chipset also supports Wake on , Stop Grant, Suspend to RAM, Suspend to Disk, and Soft...that was used for remote administration and troubleshooting. A new chipset component interconnect, the hub interface, is the third generation desktop chipset designed for Intel's SC242 architecture and the first chipset to main memory. This removes many of the conflicts experienced when installing hardware and ...
Design Guide
Page 20
... instruction, multiple data) Extensions. By placing the I/O bridge on the PCI bus by the I /O requirements will begin to -RAM. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MHz operation; In conjunction with Direct Rambus* and...bandwidth of PCI, the hub architecture ensures that the I/O subsystem, both the I /O features (IDE, AC'97, USB, etc.), receives adequate bandwidth. Intel MMX™ technology provides integer SIMD extensions. Introduction 1.4 1.4.1 1.4.2 1.4.3 1.4.4 Platform Initiatives Direct Rambus* The Direct Rambus* (RDRAM) initiative provides the ...
... instruction, multiple data) Extensions. By placing the I/O bridge on the PCI bus by the I /O requirements will begin to -RAM. The MCH RDRAM interface supports 266 MHz, 300 MHz, 356 MHz, and 400 MHz operation; In conjunction with Direct Rambus* and...bandwidth of PCI, the hub architecture ensures that the I/O subsystem, both the I /O features (IDE, AC'97, USB, etc.), receives adequate bandwidth. Intel MMX™ technology provides integer SIMD extensions. Introduction 1.4 1.4.1 1.4.2 1.4.3 1.4.4 Platform Initiatives Direct Rambus* The Direct Rambus* (RDRAM) initiative provides the ...
Design Guide
Page 37
.... The Vterm power island should be supplied during suspend-to be less than 3". Figure 2-13. Direct RDRAM Termination Terminator R-packs RSL Signals Vterm Intel®820 Chipset Design Guide 2-11 Length matching in this section of the channel opposite the MCH. This voltage does not need to... -RAM. The trace length between the last RIMM and the termination resistors should be decoupled using 27Ω-2% or 28Ω-1% resistors at LEAST ...
.... The Vterm power island should be supplied during suspend-to be less than 3". Figure 2-13. Direct RDRAM Termination Terminator R-packs RSL Signals Vterm Intel®820 Chipset Design Guide 2-11 Length matching in this section of the channel opposite the MCH. This voltage does not need to... -RAM. The trace length between the last RIMM and the termination resistors should be decoupled using 27Ω-2% or 28Ω-1% resistors at LEAST ...
Design Guide
Page 52
... N 3 3 2 2 1 A36 SOUT 1 A36 SOUT SIN B36 2.2KΩ - B 10KΩ 0.4" - 0.45" Suspend-to-RAM Shunt Transistor When an Intel® 820 chipset system enters or exits Suspend-to-RAM, power will be routed from RIMM to -RAM. In addition, to the MCH (i.e., it will be tied to ) is entering and exiting Suspend... due to the CMOS interface being driven during power ramp, the SCK (CMOS clock) signal must be powering-up or powering-down). The motherboard routing lengths for the SIO signal are the same as shown in Figure 2-28. The SIO signal requires a 2.2 KΩ - 10 ...
... N 3 3 2 2 1 A36 SOUT 1 A36 SOUT SIN B36 2.2KΩ - B 10KΩ 0.4" - 0.45" Suspend-to-RAM Shunt Transistor When an Intel® 820 chipset system enters or exits Suspend-to-RAM, power will be routed from RIMM to -RAM. In addition, to the MCH (i.e., it will be tied to ) is entering and exiting Suspend... due to the CMOS interface being driven during power ramp, the SCK (CMOS clock) signal must be powering-up or powering-down). The motherboard routing lengths for the SIO signal are the same as shown in Figure 2-28. The SIO signal requires a 2.2 KΩ - 10 ...
Design Guide
Page 93
...), by providing six REQ#/GNT# pairs. PCI Bus Layout Example ICH 2.20 RTC The ICH contains a real time clock (RTC) with a PCI REQ#/GNT# pair. Intel®820 Chipset Design Guide 2-67 The internal RTC module provides two key functions: keeping date and time, and storing system data in its... RAM when the system is used for the ICH. Figure 2-55. This section will present the recommended hookup for the RTC circuit for the PIIX4. Layout/...
...), by providing six REQ#/GNT# pairs. PCI Bus Layout Example ICH 2.20 RTC The ICH contains a real time clock (RTC) with a PCI REQ#/GNT# pair. Intel®820 Chipset Design Guide 2-67 The internal RTC module provides two key functions: keeping date and time, and storing system data in its... RAM when the system is used for the ICH. Figure 2-55. This section will present the recommended hookup for the RTC circuit for the PIIX4. Layout/...
Design Guide
Page 95
...an example of the battery can be reverse biased when the system power is used in a desktop system to provide continuous power to the RTC when available, which will be at least: 170...the diodes are set to be calculated by dividing the capacity by the system. Intel®820 Chipset Design Guide 2-69 High accuracy can give many years of ...Battery Connection The RTC requires an external battery connection to maintain its functionality and its RAM while the ICH is available. use a filter, such as possible; The battery... side of the board). • The oscillator VCC should be used .
...an example of the battery can be reverse biased when the system power is used in a desktop system to provide continuous power to the RTC when available, which will be at least: 170...the diodes are set to be calculated by dividing the capacity by the system. Intel®820 Chipset Design Guide 2-69 High accuracy can give many years of ...Battery Connection The RTC requires an external battery connection to maintain its functionality and its RAM while the ICH is available. use a filter, such as possible; The battery... side of the board). • The oscillator VCC should be used .
Design Guide
Page 153
...power rail using a voltage regulator (on the Intel® 820 Chipset Reference Board, 3.3VSB is used in the Reference Board (refer to Appendix A, "Reference Design Schematics: Uni-Processor" or Appendix B, "Reference Design Schematics: Dual-Processor") to -RAM (S3) and Soft-off . Derived power rail...are created with voltage regulators on the Intel® 820 Chipset Reference Board. Suspend operation During suspend operation, power is derived from 5V_DUAL). The core power rails that are distributed directly from some components on the motherboard. Dual power rail A dual power rail...
...power rail using a voltage regulator (on the Intel® 820 Chipset Reference Board, 3.3VSB is used in the Reference Board (refer to Appendix A, "Reference Design Schematics: Uni-Processor" or Appendix B, "Reference Design Schematics: Dual-Processor") to -RAM (S3) and Soft-off . Derived power rail...are created with voltage regulators on the Intel® 820 Chipset Reference Board. Suspend operation During suspend operation, power is derived from 5V_DUAL). The core power rails that are distributed directly from some components on the motherboard. Dual power rail A dual power rail...
Design Guide
Page 154
...) Processor | CMOS P/Us: 2.5V PCI 3.3Vaux: 3.3V 1.5A S0, S1; 435ma S3, S5 LPC Super I /O power is accounted for the Intel® 820 Chipset Reference Board. This power delivery architecture supports the "Instantly Available PC Design Guidelines" via 3.3V aux) and USB (USB can only be compared against the...by the power supply. Due to -RAM (STR) state. It is necessary to consider the effect of main memory and PCI 3.3V aux (and possibly other devices in full-power. However, only one will be OFF in S5) LEGEND: ATX Power Planes Intel® 820 Chipset Power Planes 5VSB...
...) Processor | CMOS P/Us: 2.5V PCI 3.3Vaux: 3.3V 1.5A S0, S1; 435ma S3, S5 LPC Super I /O power is accounted for the Intel® 820 Chipset Reference Board. This power delivery architecture supports the "Instantly Available PC Design Guidelines" via 3.3V aux) and USB (USB can only be compared against the...by the power supply. Due to -RAM (STR) state. It is necessary to consider the effect of main memory and PCI 3.3V aux (and possibly other devices in full-power. However, only one will be OFF in S5) LEGEND: ATX Power Planes Intel® 820 Chipset Power Planes 5VSB...
Design Guide
Page 155
... powered during Suspend-to-RAM and therefore, the VCMOS rail can be 36 Ω (top) / 100 Ω (bottom). The requirements for each power plane are met using capacitors on the voltage regulator used to lower voltages). On the Intel® 820 chipset Reference Board, the only devices connected...RDRAM core and the VCMOS rail on the board. It is less than 50 mV. System Design Considerations In addition to the power planes provided by the ATX power supply, an instantly available Intel® 820 chipset based system (using Suspend-to-RAM) requires 7 power planes to power the ...
... powered during Suspend-to-RAM and therefore, the VCMOS rail can be 36 Ω (top) / 100 Ω (bottom). The requirements for each power plane are met using capacitors on the voltage regulator used to lower voltages). On the Intel® 820 chipset Reference Board, the only devices connected...RDRAM core and the VCMOS rail on the board. It is less than 50 mV. System Design Considerations In addition to the power planes provided by the ATX power supply, an instantly available Intel® 820 chipset based system (using Suspend-to-RAM) requires 7 power planes to power the ...
Design Guide
Page 157
...current during initialization (Section 6.1.3.1, "Option 1: Reduce the Clock Frequency During Initialization" on the voltage sequencing requirements, refer to the latest Intel® 820 Chipset: 82820 Memory Controller Hub (MCH) datasheet. 3.3VSB The 3.3VSB plane powers the suspend well of the ICH ...2.5VSBY (and controlled by SLP_S3#). For further details on page 6-6); 2. The 3.3Vaux requirement state that does not support Suspendto-RAM (STR). 6.1.3 64/72Mbit RDRAM Excessive Power Consumption Some 64/72Mbit RDRAM devices interpret non-broadcast, device-directed commands as broadcast ...
...current during initialization (Section 6.1.3.1, "Option 1: Reduce the Clock Frequency During Initialization" on the voltage sequencing requirements, refer to the latest Intel® 820 Chipset: 82820 Memory Controller Hub (MCH) datasheet. 3.3VSB The 3.3VSB plane powers the suspend well of the ICH ...2.5VSBY (and controlled by SLP_S3#). For further details on page 6-6); 2. The 3.3Vaux requirement state that does not support Suspendto-RAM (STR). 6.1.3 64/72Mbit RDRAM Excessive Power Consumption Some 64/72Mbit RDRAM devices interpret non-broadcast, device-directed commands as broadcast ...
Design Guide
Page 160
... Glue Chip) To reduce the component count and BOM cost of the Intel® 820 chipset platform, Intel has developed an ASIC component that integrates miscellaneous platform logic into a single device, overall board cost can be reduced. The Glue Chip 3 is available from the following... functions into a single device. Features • PWROK signal generation • Control circuitry for Suspend To RAM ...
... Glue Chip) To reduce the component count and BOM cost of the Intel® 820 chipset platform, Intel has developed an ASIC component that integrates miscellaneous platform logic into a single device, overall board cost can be reduced. The Glue Chip 3 is available from the following... functions into a single device. Features • PWROK signal generation • Control circuitry for Suspend To RAM ...
Design Guide
Page 210
...R182 20 51-1% 18 R185 CLKTM 51-1% R200 13 C80 CLKTM_RD 39-1% DRCG_CLKB# R205 CLKTM# 13 No stuff C80 C205 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: CLOCK SYNTHESIZER 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET:...C204 C220 C209 0.1UF 0.1UF 0.1UF 0.1UF 10UF VDDIR 1 VDDIPD 10 VDDO1 16 VDDO2 22 VDDP 3 VDDC 9 R219 10K R204 10K R199 10K B HOST BUS /RAM BUS JP 13 100/300 2 -3 100/400 OUT 133/400 2 -3 G P O CNTRL* 1 -2 JP 18 OUT OUT OUT OUT VCC3_3 MULT0_GPIO 11 JP13 ...
...R182 20 51-1% 18 R185 CLKTM 51-1% R200 13 C80 CLKTM_RD 39-1% DRCG_CLKB# R205 CLKTM# 13 No stuff C80 C205 A TITLE: INTEL(R) 820 CHIPSET DUAL PROCESSOR CUSTOMER REFERENCE BOARD REV: CLOCK SYNTHESIZER 3.03 R PCD PLATFORM DESIGN DRAWN BY: PROJECT: 1900 PRAIRIE CITY ROAD FOLSOM, CALIFORNIA 95630 LAST REVISED: SHEET:...C204 C220 C209 0.1UF 0.1UF 0.1UF 0.1UF 10UF VDDIR 1 VDDIPD 10 VDDO1 16 VDDO2 22 VDDP 3 VDDC 9 R219 10K R204 10K R199 10K B HOST BUS /RAM BUS JP 13 100/300 2 -3 100/400 OUT 133/400 2 -3 G P O CNTRL* 1 -2 JP 18 OUT OUT OUT OUT VCC3_3 MULT0_GPIO 11 JP13 ...