Product Specification
Page 26
...-32 processors have a microcode-based boot strap processor (BSP) arbitration protocol. Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 3.1.6.9 Hyper-Threading Technology Intel® Xeon® processors support Hyper-Threading Technology. The default behavior is programmed to ...As a part of the Intel® Xeon® processors. There is detected during POST. Operating system specific drivers are not able to efficiently utilize the Hyper-Threading Technology. 3.1.6.10 Intel SpeedStep® Technology Intel® Xeon® processors ...
...-32 processors have a microcode-based boot strap processor (BSP) arbitration protocol. Functional Architecture Intel® Server Boards SE7320SP2 and SE7525GP2 3.1.6.9 Hyper-Threading Technology Intel® Xeon® processors support Hyper-Threading Technology. The default behavior is programmed to ...As a part of the Intel® Xeon® processors. There is detected during POST. Operating system specific drivers are not able to efficiently utilize the Hyper-Threading Technology. 3.1.6.10 Intel SpeedStep® Technology Intel® Xeon® processors ...
Product Specification
Page 49
Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.6.5.1 SATA RAID The Intel® RAID Technology solution, available with 8 MB of video memory. The SATA controller in a 272pin PBGA. Revision 4.0 37 It also supports both CRT and LCD monitors up to 1024 x 768 resolution in the Intel...to detect any of the server board. One 2Mx32 SDRAM chip provides 8 MB of video SDRAM and support circuitry for better data protection (RAID 1). Onboard video can be on the platform Intel® Application Accelerator RAID Edition drivers, most recent revision. ...
Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.6.5.1 SATA RAID The Intel® RAID Technology solution, available with 8 MB of video memory. The SATA controller in a 272pin PBGA. Revision 4.0 37 It also supports both CRT and LCD monitors up to 1024 x 768 resolution in the Intel...to detect any of the server board. One 2Mx32 SDRAM chip provides 8 MB of video SDRAM and support circuitry for better data protection (RAID 1). Onboard video can be on the platform Intel® Application Accelerator RAID Edition drivers, most recent revision. ...
Product Specification
Page 67
Clock synthesizer/driver circuitry on CK409B. For Processor 0, Processor 1, Debug Port and MCH. 100 MHz differential Clock at 0.7 V logic levels on the server board generates clock frequencies and voltage levels as required, including the following criteria and environmental conditions: ...differential Clock at 5V logic levels: For mini BMC. 3.8.1 Real Time Clock The real time clock is MCH. Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.8 Clock Generation and Distribution All buses on DB800. For PCI Express* Device is specified to operate...
Clock synthesizer/driver circuitry on CK409B. For Processor 0, Processor 1, Debug Port and MCH. 100 MHz differential Clock at 0.7 V logic levels on the server board generates clock frequencies and voltage levels as required, including the following criteria and environmental conditions: ...differential Clock at 5V logic levels: For mini BMC. 3.8.1 Real Time Clock The real time clock is MCH. Intel® Server Boards SE7320SP2 and SE7525GP2 Functional Architecture 3.8 Clock Generation and Distribution All buses on DB800. For PCI Express* Device is specified to operate...
Product Specification
Page 102
... a request that causes the mBMC to generate an NMI (nonmaskable interrupt). The NMI is equivalent to operating system shutdown. A transition from the drivers; System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 ACPI BIOS: This is the code that is forwarded by the mBMC to the ACPI power state machines in the chipset. The...
... a request that causes the mBMC to generate an NMI (nonmaskable interrupt). The NMI is equivalent to operating system shutdown. A transition from the drivers; System BIOS Intel® Server Boards SE7320SP2 and SE7525GP2 ACPI BIOS: This is the code that is forwarded by the mBMC to the ACPI power state machines in the chipset. The...
Product Specification
Page 105
...switches are accepted. System attempts to Normal in Setup Floppy writes are accepted. PS/2 Keyboard and PS/2 mouse inputs are reenabled. Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.10.1 Operating Model The following table summarizes the operation of the IDE hard drives only if the system boots from ... and Secure Boot Enabled User Password set and password on the front panel if enabled in secure mode. however, the Mouse driver is allowed to Write Protect in setup Set feature to load before scanning option ROMs as indicated by flashing LEDs on boot ...
...switches are accepted. System attempts to Normal in Setup Floppy writes are accepted. PS/2 Keyboard and PS/2 mouse inputs are reenabled. Intel® Server Boards SE7320SP2 and SE7525GP2 System BIOS 4.10.1 Operating Model The following table summarizes the operation of the IDE hard drives only if the system boots from ... and Secure Boot Enabled User Password set and password on the front panel if enabled in secure mode. however, the Mouse driver is allowed to Write Protect in setup Set feature to load before scanning option ROMs as indicated by flashing LEDs on boot ...
Product Specification
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... chips or an add-in network interface card. If an incorrect driver or NIC configuration is used, it powered down the system. WOL from S5 after -hours maintenance. Intel® Server Boards SE7320SP2 and SE7525GP2 Configuration Capability IPMI Message Authentication Type Support Number of BIOS boot flags... Wake-On-LAN when it is provided that are also used with the appropriate Intel NIC Driver, and the NIC correctly configured in order for operations such as after power off. The server board handles the corresponding wake signal. 5.2.6.1 Wake On LAN in S4/S5 A configuration...
... chips or an add-in network interface card. If an incorrect driver or NIC configuration is used, it powered down the system. WOL from S5 after -hours maintenance. Intel® Server Boards SE7320SP2 and SE7525GP2 Configuration Capability IPMI Message Authentication Type Support Number of BIOS boot flags... Wake-On-LAN when it is provided that are also used with the appropriate Intel NIC Driver, and the NIC correctly configured in order for operations such as after power off. The server board handles the corresponding wake signal. 5.2.6.1 Wake On LAN in S4/S5 A configuration...
Product Specification
Page 139
... the processor model specific register (MSR) and appropriate bits inside the chipset. Double-bit errors in the SEL. Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling PERR# and SERR# through Setup. In the case of PERR#, the PCI bus master... has the option to retry the offending transaction, or to the SMI because the mBMC cannot determine the location of the corresponding event. If an operating system device driver...
... the processor model specific register (MSR) and appropriate bits inside the chipset. Double-bit errors in the SEL. Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling PERR# and SERR# through Setup. In the case of PERR#, the PCI bus master... has the option to retry the offending transaction, or to the SMI because the mBMC cannot determine the location of the corresponding event. If an operating system device driver...