Product Specification
Page 2
... names may appear in this document or any intellectual property rights is furnished for use in connection with this manual is granted by Intel Corporation. Updated supported processors matrix and BIOS setup options according to new 3.0 BIOS release, modified front panel ... changes to specifications and product descriptions at any patent, copyright or other intellectual property right. Revision History Intel® Server Boards SE7320SP2 and SE7525GP2 Revision History Date June 2004 November 2004 September 2005 December 2005 Revision Number Modifications 1.0 Initial Release 2.0 ...
... names may appear in this document or any intellectual property rights is furnished for use in connection with this manual is granted by Intel Corporation. Updated supported processors matrix and BIOS setup options according to new 3.0 BIOS release, modified front panel ... changes to specifications and product descriptions at any patent, copyright or other intellectual property right. Revision History Intel® Server Boards SE7320SP2 and SE7525GP2 Revision History Date June 2004 November 2004 September 2005 December 2005 Revision Number Modifications 1.0 Initial Release 2.0 ...
Product Specification
Page 43
... server boards implement a x8 PCI Express connector on the secondary side of x4 (2 GB/s). 3.6.1.4 P64-Express16: x16 PCI Express bus segment Intel® Server Board SE7525GP2 only: The P64-Express16 bus segment supports x16 PCI Express signaling. 3.6.1.5 Scan Order The BIOS assigns PCI bus numbers in a depth-first ...the BIOS will dispatch the option ROMs in available memory space in accordance with respect to them. If a bridge is provided to manually configure the IRQs for the devices that will operate at a maximum speed of the bridge until all rules with the PCI Local Bus ...
... server boards implement a x8 PCI Express connector on the secondary side of x4 (2 GB/s). 3.6.1.4 P64-Express16: x16 PCI Express bus segment Intel® Server Board SE7525GP2 only: The P64-Express16 bus segment supports x16 PCI Express signaling. 3.6.1.5 Scan Order The BIOS assigns PCI bus numbers in a depth-first ...the BIOS will dispatch the option ROMs in available memory space in accordance with respect to them. If a bridge is provided to manually configure the IRQs for the devices that will operate at a maximum speed of the bridge until all rules with the PCI Local Bus ...
Product Specification
Page 147
...table. Detects the presence of KB/MS using AMI KB-5. Initializes different devices through DIM. Revision 4.0 135 Verify CMOS checksum manually by reading storage area. Init Local APIC Set up boot strap processor Information Set up boot strap processor for POST Enumerate ...after Auto detection of Keyboard in PIC for system timer interrupt. Initializes the CPU. Also, update the Kernel Variables. Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling 6.3.3 POST Code Checkpoints Table 65. Initialize BIOS, POST, Run-time data area. Disable Cache...
...table. Detects the presence of KB/MS using AMI KB-5. Initializes different devices through DIM. Revision 4.0 135 Verify CMOS checksum manually by reading storage area. Init Local APIC Set up boot strap processor Information Set up boot strap processor for POST Enumerate ...after Auto detection of Keyboard in PIC for system timer interrupt. Initializes the CPU. Also, update the Kernel Variables. Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling 6.3.3 POST Code Checkpoints Table 65. Initialize BIOS, POST, Run-time data area. Disable Cache...
Product Specification
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...Table 69. Static resources are set to initialize different buses. Function 3 searches for and configures all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCI-PCI bridges, and noncompliant PCI devices. ACPI Runtime Checkpoints Checkpoint ... an automatic configuration and configures all device nodes, PCI devices, and PnP ISA cards. Revision 4.0 139 Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling The flash has been updated successfully. Make flash write disabled. Boot Output Device Initialization...
...Table 69. Static resources are set to initialize different buses. Function 3 searches for and configures all static devices that include manual configured onboard peripherals, memory and I/O decode windows in PCI-PCI bridges, and noncompliant PCI devices. ACPI Runtime Checkpoints Checkpoint ... an automatic configuration and configures all device nodes, PCI devices, and PnP ISA cards. Revision 4.0 139 Intel® Server Boards SE7320SP2 and SE7525GP2 Error Reporting and Handling The flash has been updated successfully. Make flash write disabled. Boot Output Device Initialization...