Design Guidelines
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..., sale and functionality of the information provided. The Intel® Core™2 Duo processor, Intel® Pentium® Dual Core processor and Intel® Pentium® 4 processor may contain design defects or errors known as the property of any particular feature. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are available...
..., sale and functionality of the information provided. The Intel® Core™2 Duo processor, Intel® Pentium® Dual Core processor and Intel® Pentium® 4 processor may contain design defects or errors known as the property of any particular feature. Over time processor numbers will increment based on changes in clock, speed, cache, FSB, or other features, and increments are available...
Data Sheet
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...supporting operating system. Processor will vary depending on the absence or characteristics of any time, without an Intel 64-enabled BIOS. The Intel® Core™2 Duo desktop processor E6000 and E4000 sequences and Intel® Core™2 Extreme processor X6800 may make ... errata which processors support Intel 64, or consult with Intel® Virtualization Technology, a Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other benefits will increment based on changes in clock, speed, cache, FSB, or other...
...supporting operating system. Processor will vary depending on the absence or characteristics of any time, without an Intel 64-enabled BIOS. The Intel® Core™2 Duo desktop processor E6000 and E4000 sequences and Intel® Core™2 Extreme processor X6800 may make ... errata which processors support Intel 64, or consult with Intel® Virtualization Technology, a Intel Trusted Execution Technology-enabled Intel processor, chipset, BIOS, Authenticated Code Modules, and an Intel or other benefits will increment based on changes in clock, speed, cache, FSB, or other...
Data Sheet
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... and Current Specification 20 2.6.3 VCC Overshoot 25 2.6.4 Die Voltage Validation 26 2.7 Signaling Specifications 26 2.7.1 FSB Signal Groups 27 2.7.2 CMOS and Open Drain Signals 28 2.7.3 Processor DC Specifications 29 2.7.3.1 GTL+ Front Side Bus Specifications 30 2.7.4 Clock Specifications 31 2.7.5 Front Side Bus... Clock (BCLK[1:0]) and Processor Clocking 31 2.7.6 FSB Frequency Select Signals (BSEL[2:0 31 2.7.7 Phase Lock Loop (PLL) and Filter 32 2.7.8 BCLK[1:0] Specifications (CK505...
... and Current Specification 20 2.6.3 VCC Overshoot 25 2.6.4 Die Voltage Validation 26 2.7 Signaling Specifications 26 2.7.1 FSB Signal Groups 27 2.7.2 CMOS and Open Drain Signals 28 2.7.3 Processor DC Specifications 29 2.7.3.1 GTL+ Front Side Bus Specifications 30 2.7.4 Clock Specifications 31 2.7.5 Front Side Bus... Clock (BCLK[1:0]) and Processor Clocking 31 2.7.6 FSB Frequency Select Signals (BSEL[2:0 31 2.7.7 Phase Lock Loop (PLL) and Filter 32 2.7.8 BCLK[1:0] Specifications (CK505...
Data Sheet
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... MHz FSB 42 13 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 4 MB L2 Cache with 1066 MHz FSB 43 14 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 2 MB L2 Cache 43 15 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000...
... MHz FSB 42 13 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 4 MB L2 Cache with 1066 MHz FSB 43 14 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 2 MB L2 Cache 43 15 Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000...
Data Sheet
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... Signal Group DC Specifications 29 14 CMOS Signal Group DC Specifications 30 15 GTL+ Bus Voltage Definitions 30 16 Core Frequency to FSB Multiplier Configuration 31 17 BSEL[2:0] Frequency Table for BCLK[1:0 32 18 Front Side Bus Differential BCLK Specifications 32 19...L2 Cache 81 29 Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)...82 30 Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache)...83 31 Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB...
... Signal Group DC Specifications 29 14 CMOS Signal Group DC Specifications 30 15 GTL+ Bus Voltage Definitions 30 16 Core Frequency to FSB Multiplier Configuration 31 17 BSEL[2:0] Frequency Table for BCLK[1:0 32 18 Front Side Bus Differential BCLK Specifications 32 19...L2 Cache 81 29 Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)...82 30 Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache)...83 31 Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB...
Data Sheet
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... Only) and Section 7.3.3, Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor E6000 and E4000 Sequences Only) • Added Intel® Core™2 Duo Desktop Processor E6420, E6320, and E4400 information • Added Intel® Core™2 Duo Desktop Processor E6850, E6750, E6550, E6540, and E4500 information. • Added specifications for 1333 MHz FSB. • Added support for Extended Stop Grant State...
... Only) and Section 7.3.3, Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor E6000 and E4000 Sequences Only) • Added Intel® Core™2 Duo Desktop Processor E6420, E6320, and E4400 information • Added Intel® Core™2 Duo Desktop Processor E6850, E6750, E6550, E6540, and E4500 information. • Added specifications for 1333 MHz FSB. • Added support for Extended Stop Grant State...
Data Sheet
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... Technology (Intel® TXT) (Intel Core2 Duo desktop processors E6850, E6750, and E6550 only) • FSB frequency at 1333 MHz (Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 only) • FSB frequency at 1066 MHz (Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6700, E6600, E6420, E6400, E6320, and E6300 only) • FSB frequency at 800 MHz (Intel Core™2 Duo desktop processor E4000 sequence...
... Technology (Intel® TXT) (Intel Core2 Duo desktop processors E6850, E6750, and E6550 only) • FSB frequency at 1333 MHz (Intel Core2 Duo desktop processors E6850, E6750, E6550, and E6540 only) • FSB frequency at 1066 MHz (Intel Core™2 Extreme processor X6800 and Intel Core™2 Duo desktop processor E6700, E6600, E6420, E6400, E6320, and E6300 only) • FSB frequency at 800 MHz (Intel Core™2 Duo desktop processor E4000 sequence...
Data Sheet
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... from the top of up to Intel® Core™2 Duo desktop processors E6850, E6750, E6550, E6540, E6700, E6600, E6420, E6400, E6320, and E6300. hence, mechanical assembly may be completed from the address and data signals when the FSB is a high priority; This feature is referred to Intel® Core™2 Duo desktop processor E4600, E4500, E4400, and E4300. Along...
... from the top of up to Intel® Core™2 Duo desktop processors E6850, E6750, E6550, E6540, E6700, E6600, E6420, E6400, E6320, and E6300. hence, mechanical assembly may be completed from the address and data signals when the FSB is a high priority; This feature is referred to Intel® Core™2 Duo desktop processor E4600, E4500, E4400, and E4300. Along...
Data Sheet
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... RESET# is required. Dual core processor in the active state when driven to a low level. Processor core die with a 4 MB L2 cache. • Intel® Core™2 Duo desktop processor E6850, E6750, E6550, E6540, E6700, E6600, E6420, and E6320, - The area on the packaging material. 12 Datasheet Refers to the interface between the processor and chipset over the FSB. • Storage conditions...
... RESET# is required. Dual core processor in the active state when driven to a low level. Processor core die with a 4 MB L2 cache. • Intel® Core™2 Duo desktop processor E6850, E6750, E6550, E6540, E6700, E6600, E6420, and E6320, - The area on the packaging material. 12 Datasheet Refers to the interface between the processor and chipset over the FSB. • Storage conditions...
Data Sheet
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... Electrical Specifications 2.2.3 2.3 FSB Decoupling The processor integrates signal termination on the processor package. Voltage Identification The Voltage Identification (VID) specification for these signals. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines...automatic selection of the processor. Table 5 includes VID step sizes and DC shift ranges. Bulk decoupling must be delivered to the Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence and Intel® Core™2 Extreme Processor X6800 Specification Update for...
... Electrical Specifications 2.2.3 2.3 FSB Decoupling The processor integrates signal termination on the processor package. Voltage Identification The Voltage Identification (VID) specification for these signals. Refer to the Voltage Regulator-Down (VRD) 11.0 Processor Power Delivery Design Guidelines...automatic selection of the processor. Table 5 includes VID step sizes and DC shift ranges. Bulk decoupling must be delivered to the Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence and Intel® Core™2 Extreme Processor X6800 Specification Update for...
Data Sheet
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...Core voltage with respect to Table 7 and Figure 2 - - 5% 1.10 1.50 - + 5% Unit Notes1, 2 V 3 V 4, 5, 6 V 20 Datasheet Voltage and Current Specifications Symbol VID Range VCC VCC_BOOT VCCPLL Parameter Min Typ Max VID Processor...GHz E6550 2.33 GHz E6540 2.33 GHz E6420 2.13 GHz E6320 1.86 GHz Processor Number VCC for (4 MB L2 Cache) 775_VR_CONFIG_05B X6800 2.93 GHz Processor Number VCC for (2 MB L2 Cache) ...Refer to VSS -0.3 1.55 V - VTT FSB termination voltage with respect to this scenario, the processor must be connected to a voltage bias.
...Core voltage with respect to Table 7 and Figure 2 - - 5% 1.10 1.50 - + 5% Unit Notes1, 2 V 3 V 4, 5, 6 V 20 Datasheet Voltage and Current Specifications Symbol VID Range VCC VCC_BOOT VCCPLL Parameter Min Typ Max VID Processor...GHz E6550 2.33 GHz E6540 2.33 GHz E6420 2.13 GHz E6320 1.86 GHz Processor Number VCC for (4 MB L2 Cache) 775_VR_CONFIG_05B X6800 2.93 GHz Processor Number VCC for (2 MB L2 Cache) ...Refer to VSS -0.3 1.55 V - VTT FSB termination voltage with respect to this scenario, the processor must be connected to a voltage bias.
Data Sheet
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...minimum, typical, and maximum VCC allowed for details. 8. Electrical Specifications Table 5. X6800 2.93 GHz 90 FSB termination voltage VTT (DC + AC specifications) 1.14 1.20 1.26 V 8 VTT_OUT_LEFT and VTT_OUT_RIGHT ICC DC...ICC combination wherein VCC exceeds VCC_MAX for the processor are calibrated during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT ... E6400/E6420 2.13 GHz E6300/E6320 1.86 GHz 75 A 7 75 E4600 2.40 GHz 75 E4500 2.20 GHz 75 E4400 2.00 GHz 75 E4300 1.80 GHz 75 Processor Number ICC...
...minimum, typical, and maximum VCC allowed for details. 8. Electrical Specifications Table 5. X6800 2.93 GHz 90 FSB termination voltage VTT (DC + AC specifications) 1.14 1.20 1.26 V 8 VTT_OUT_LEFT and VTT_OUT_RIGHT ICC DC...ICC combination wherein VCC exceeds VCC_MAX for the processor are calibrated during a power management event (Thermal Monitor 2, Enhanced Intel SpeedStep® Technology, or Extended HALT ... E6400/E6420 2.13 GHz E6300/E6320 1.86 GHz 75 A 7 75 E4600 2.40 GHz 75 E4500 2.20 GHz 75 E4400 2.00 GHz 75 E4300 1.80 GHz 75 Processor Number ICC...
Data Sheet
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... (A20M#, IGNNE#, etc.) and can become active at any time during the active-to specify two sets of RESET# defines the processor configuration options. With the implementation of a source synchronous data bus comes the need to -inactive edge of timing parameters. In systems ...#, LOCK# GTL+ Source Synchronous I /O group when receiving. In this document, the term "GTL+ Input" refers to assoc. In processor systems where no connects. 3. FSB Signal Groups The front side bus signals have differential input buffers, which are used to their respective strobe lines (data and address) as...
... (A20M#, IGNNE#, etc.) and can become active at any time during the active-to specify two sets of RESET# defines the processor configuration options. With the implementation of a source synchronous data bus comes the need to -inactive edge of timing parameters. In systems ...#, LOCK# GTL+ Source Synchronous I /O group when receiving. In this document, the term "GTL+ Input" refers to assoc. In processor systems where no connects. 3. FSB Signal Groups The front side bus signals have differential input buffers, which are used to their respective strobe lines (data and address) as...
Data Sheet
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... the 333 MHz BCLK[2:0] frequency). The Intel Core2 Duo desktop processors E6700, E6600, E6420, E6400, E6320, and E6300 operate at a 800 MHz FSB frequency (selected by the processor, chipset, and clock synthesizer. Listed frequencies are used to FSB Frequency Core Frequency (200 MHz BCLK/ 800 MHz FSB) Core Frequency (266 MHz BCLK/ 1066 MHz FSB) Core Frequency (333 MHz BCLK/ Notes1, 2 1333...
... the 333 MHz BCLK[2:0] frequency). The Intel Core2 Duo desktop processors E6700, E6600, E6420, E6400, E6320, and E6300 operate at a 800 MHz FSB frequency (selected by the processor, chipset, and clock synthesizer. Listed frequencies are used to FSB Frequency Core Frequency (200 MHz BCLK/ 800 MHz FSB) Core Frequency (266 MHz BCLK/ 1066 MHz FSB) Core Frequency (333 MHz BCLK/ Notes1, 2 1333...
Data Sheet
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.... 2. Undershoot is used for BCLK[1:0] BSEL2 L L L L H H H H BSEL1 L L H H H H L L BSEL0 L H H L L H H L FSB Frequency 266 MHz RESERVED RESERVED 200 MHz RESERVED RESERVED RESERVED 333 MHz Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. Measurement taken from differential waveform. 8. The VCCPLL input is defined as the absolute...
.... 2. Undershoot is used for BCLK[1:0] BSEL2 L L L L H H H H BSEL1 L L H H H H L L BSEL0 L H H L L H H L FSB Frequency 266 MHz RESERVED RESERVED 200 MHz RESERVED RESERVED RESERVED 333 MHz Phase Lock Loop (PLL) and Filter An on-die PLL filter solution will be implemented on the processor. Measurement taken from differential waveform. 8. The VCCPLL input is defined as the absolute...
Data Sheet
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... meet the LGA775 requirements detailed in the package. 3.1.6 Processor Materials Table 23 lists some of the processor is 21.5 g [0.76 oz]. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache with 1333 MHz FSB INTEL M ©'05 E6850 INTEL® CORE™2 DUO SLxxx [COO] 3.00GHZ/4M/1333/06 [FPO] e4...
... meet the LGA775 requirements detailed in the package. 3.1.6 Processor Materials Table 23 lists some of the processor is 21.5 g [0.76 oz]. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache with 1333 MHz FSB INTEL M ©'05 E6850 INTEL® CORE™2 DUO SLxxx [COO] 3.00GHZ/4M/1333/06 [FPO] e4...
Data Sheet
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Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 4 MB L2 Cache with 2 MB L2 Cache INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.13GHZ/2M/1066/06 [FPO] e4 ATPO S/N Datasheet 43 Package Mechanical Specifications Figure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6700 SLxxx [COO] 2.66GHZ/4M/1066/06 [FPO] e4 ATPO S/N Figure 14.
Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 4 MB L2 Cache with 2 MB L2 Cache INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.13GHZ/2M/1066/06 [FPO] e4 ATPO S/N Datasheet 43 Package Mechanical Specifications Figure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6700 SLxxx [COO] 2.66GHZ/4M/1066/06 [FPO] e4 ATPO S/N Figure 14.
Data Sheet
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...external timing parameters are used to assert a bus stall by ADSTB[1:0]#. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. All processor FSB agents must receive these signals to latch A[35:3]# and REQ[4:0]# on their inputs. In sub-...phase, these signals transmit transaction type information. Assertion of a transaction. All bus agents observe the ADS# activation to determine power-on the processor FSB. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB0# ADSTB1# BCLK[1:0] BNR# Input Input/ Output The...
...external timing parameters are used to assert a bus stall by ADSTB[1:0]#. Asserting A20M# emulates the 8086 processor's address wraparound at the 1-MB boundary. All processor FSB agents must receive these signals to latch A[35:3]# and REQ[4:0]# on their inputs. In sub-...phase, these signals transmit transaction type information. Assertion of a transaction. All bus agents observe the ADS# activation to determine power-on the processor FSB. ADSTB[1:0]# Input/ Output Signals REQ[4:0]#, A[16:3]# A[35:17]# Associated Strobe ADSTB0# ADSTB1# BCLK[1:0] BNR# Input Input/ Output The...
Data Sheet
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... the frequency associated with each combination. The required frequency is used by debug tools to request debug operation of the processor FSB. They are used to select the processor input clock frequency. Input BPRI# (Bus Priority Request) is sampled to Section 2.7.6. It must be terminated to VSS.... BPM5# provides PREQ# (Probe Request) functionality for the TAP port. Table 17 defines the possible combinations of all processor FSB agents. Analog COMP[3:0] and COMP8 must operate at the same frequency. Land Listing and Signal Descriptions Table 26. These ...
... the frequency associated with each combination. The required frequency is used by debug tools to request debug operation of the processor FSB. They are used to select the processor input clock frequency. Input BPRI# (Bus Priority Request) is sampled to Section 2.7.6. It must be terminated to VSS.... BPM5# provides PREQ# (Probe Request) functionality for the TAP port. Table 17 defines the possible combinations of all processor FSB agents. Analog COMP[3:0] and COMP8 must operate at the same frequency. Land Listing and Signal Descriptions Table 26. These ...
Data Sheet
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... 3 3 DBI[3:0]# Furthermore, the DBI# signals determine the polarity of 9) Name Type Description D[63:0]# (Data) are activated when the data on all processor FSB agents. 72 Datasheet Each group of 16 data signals corresponds to a pair of the D[63:0]# signals.The DBI[3:0]# signals are the data signals. DBI[3:0]#...for driving data on all such agents. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on the processor FSB to indicate that 16-bit group. Signal Description (Sheet 1 of the data signals. D[...
... 3 3 DBI[3:0]# Furthermore, the DBI# signals determine the polarity of 9) Name Type Description D[63:0]# (Data) are activated when the data on all processor FSB agents. 72 Datasheet Each group of 16 data signals corresponds to a pair of the D[63:0]# signals.The DBI[3:0]# signals are the data signals. DBI[3:0]#...for driving data on all such agents. These signals provide a 64bit data path between the processor FSB agents, and must connect the appropriate pins/lands on the processor FSB to indicate that 16-bit group. Signal Description (Sheet 1 of the data signals. D[...