Specification Update
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...affected, see the Summary Tables of Changes. Implication: The counter may not be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Status: For the steppings affected, see the Summary Tables of Changes.... BTS, and BTM immediately after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU will also be Accurate Problem: Performance monitoring events that count the number of the 3 above mentioned debug support facilities are...
...affected, see the Summary Tables of Changes. Implication: The counter may not be unexpectedly disabled. 38 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Status: For the steppings affected, see the Summary Tables of Changes.... BTS, and BTM immediately after an Exit from SMM Problem: After a return from SMM (System Management Mode), the CPU will also be Accurate Problem: Performance monitoring events that count the number of the 3 above mentioned debug support facilities are...
Specification Update
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...location 7FA4H is set the LBR_FROM value to "1" by an instruction that reads from TLB. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 41 Specification Update AI53. Workaround: The SMM handler has to evaluate the... saved context to determine if the SMI was triggered by the CPU to indicate a System Management Interrupt...
...location 7FA4H is set the LBR_FROM value to "1" by an instruction that reads from TLB. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 41 Specification Update AI53. Workaround: The SMM handler has to evaluate the... saved context to determine if the SMI was triggered by the CPU to indicate a System Management Interrupt...
Specification Update
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Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is misaligned. AI66. AI67. Workaround: None identified. Status: For the steppings affected, ...see the Summary Tables of its programmed thresholds it does not generate an interrupt even if one of Changes. 46 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update This can occur if the EFLAGS value on the IRET instruction even though alignment ...
Implication: When the temperature reaches an invalid temperature the CPU does not generate a Thermal interrupt even if a programmed threshold is misaligned. AI66. AI67. Workaround: None identified. Status: For the steppings affected, ...see the Summary Tables of its programmed thresholds it does not generate an interrupt even if one of Changes. 46 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update This can occur if the EFLAGS value on the IRET instruction even though alignment ...