Specification Update
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...; Trusted Execution Technologyŧ December 2010 Notice: The Intel® CoreTM2 Extreme and Intel® CoreTM2 Duo desktop processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequence Specification Update...
...; Trusted Execution Technologyŧ December 2010 Notice: The Intel® CoreTM2 Extreme and Intel® CoreTM2 Duo desktop processor may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Intel® Core™2 Extreme Processor X6800Δ and Intel® Core™2 Duo Desktop Processor E6000Δ and E4000Δ Sequence Specification Update...
Specification Update
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... features within each processor family, not across different processor families. Intel, the Intel logo, Celeron, Pentium, Xeon, Intel SpeedStep, Intel Core, and Core Inside are available on hardware and software configurations. Intel Virtualization Technology-enabled BIOS and VMM applications are not a measure of others. Copyright © 2006 - 2010, Intel Corporation 2 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000...
... features within each processor family, not across different processor families. Intel, the Intel logo, Celeron, Pentium, Xeon, Intel SpeedStep, Intel Core, and Core Inside are available on hardware and software configurations. Intel Virtualization Technology-enabled BIOS and VMM applications are not a measure of others. Copyright © 2006 - 2010, Intel Corporation 2 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000...
Specification Update
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... -004 -005 -006 -007 -008 -009 -010 -011 -012 Description • Initial release of the Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence Specification Update • Updated Erratum AI19, AI29 and AI40 • Added Erratum AI58-AI67 • Updated...Jan 2007 Out Of Cycle Feb 2007 Mar 2007 Apr 2007 Apr 2007 Out Of Cycle 4 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI100 • Added Erratum AI101-AI104 • Updated ...
... -004 -005 -006 -007 -008 -009 -010 -011 -012 Description • Initial release of the Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 Sequence Specification Update • Updated Erratum AI19, AI29 and AI40 • Added Erratum AI58-AI67 • Updated...Jan 2007 Out Of Cycle Feb 2007 Mar 2007 Apr 2007 Apr 2007 Out Of Cycle 4 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update AI100 • Added Erratum AI101-AI104 • Updated ...
Specification Update
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...8226; Updated Erratum AI51 • Deleted Erratum AI123 (because it is repeat of AI108) and replaced with a new Erratum • Added processor number E4700 information • Added Erratum AI127, AI128 -027 • Added Erratum AI129 Date Apr 2007 Out Of Cycle May 2007 July 2007...Oct 2007 Nov 2007 Dec 2007 Jan 16th 2008 Feb 13th 2008 Mar 3rd 2008 May 2008 December 8th, 2010 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5 Specification Update AI123 • Updated Plan Status for AI33 and AI43 • Added...
...8226; Updated Erratum AI51 • Deleted Erratum AI123 (because it is repeat of AI108) and replaced with a new Erratum • Added processor number E4700 information • Added Erratum AI127, AI128 -027 • Added Erratum AI129 Date Apr 2007 Out Of Cycle May 2007 July 2007...Oct 2007 Nov 2007 Dec 2007 Jan 16th 2008 Feb 13th 2008 Mar 3rd 2008 May 2008 December 8th, 2010 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 5 Specification Update AI123 • Updated Plan Status for AI33 and AI43 • Added...
Specification Update
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...; 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide Document Location http://www.intel.com/product s/processor/manuals/index.h tm 6 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Preface Preface This document is intended for hardware system manufacturers and for software developers of...
...; 64 and IA-32 Architectures Software Developer's Manual Volume 3B: System Programming Guide Document Location http://www.intel.com/product s/processor/manuals/index.h tm 6 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Preface Preface This document is intended for hardware system manufacturers and for software developers of...
Specification Update
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... documentation (datasheets, manuals, etc.). § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 7 Specification Update The NDA specification update has a processor identification information table that stepping are modifications to be... These processors are used for that lists these circumstances, errata removed from the specification update when the appropriate changes are archived and available upon request. Errata are differentiated by their unique characteristics (e.g., core speed, L2 cache size,...
... documentation (datasheets, manuals, etc.). § Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 7 Specification Update The NDA specification update has a processor identification information table that stepping are modifications to be... These processors are used for that lists these circumstances, errata removed from the specification update when the appropriate changes are archived and available upon request. Errata are differentiated by their unique characteristics (e.g., core speed, L2 cache size,...
Specification Update
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... Summary Tables of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. Intel intends to fix some of the errata in a future stepping of Changes The following notations: Codes Used in Summary Table...apply to this erratum. Row Shaded: This item is fixed in a future stepping of the document. 8 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update There are no plans to the listed MCH steppings. This table uses ...
... Summary Tables of the component, and to account for the other outstanding issues through documentation or Specification Changes as noted. Intel intends to fix some of the errata in a future stepping of Changes The following notations: Codes Used in Summary Table...apply to this erratum. Row Shaded: This item is fixed in a future stepping of the document. 8 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update There are no plans to the listed MCH steppings. This table uses ...
Specification Update
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... = Dual-Core Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Dual-Core Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel®...
... = Dual-Core Intel® Xeon® processor 7000 sequence Intel® Celeron® processor Dual-Core Intel® Xeon® processor 2.80 GHz Intel® Pentium® III processor Intel® Pentium® processor Extreme Edition and Intel® Pentium® D processor Dual-Core Intel® Xeon® processor 5000 series 64-bit Intel® Xeon® processor MP with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Celeron® D processor Mobile Intel® Celeron® processor Intel®...
Specification Update
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... by Machine-Check Architecture (MCA) on Single-bit L2 ECC Errors May be Preempted AI8 X X X ...Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor QX9775Δ Intel® Atom™ processor Z5xx series The Specification Updates for the Pentium® processor, Pentium® Pro processor, and other Intel products do not use this convention. Summary Tables of a #GP Fault 10 Intel® Core™2 Extreme Processor X6800 and Intel...
... by Machine-Check Architecture (MCA) on Single-bit L2 ECC Errors May be Preempted AI8 X X X ...Core Intel® Xeon® processor 3300 series Dual-Core Intel® Xeon® E3110 Processor Intel® Celeron® dual-core processor E1000 series Intel® Core™2 Extreme Processor QX9775Δ Intel® Atom™ processor Z5xx series The Specification Updates for the Pentium® processor, Pentium® Pro processor, and other Intel products do not use this convention. Summary Tables of a #GP Fault 10 Intel® Core™2 Extreme Processor X6800 and Intel...
Specification Update
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... Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI10 X...AI17 X X X X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line AI18 X X X X X No Fix ...-canonical Address May have Non-deterministic Results AI23 X X X X Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field AI24...Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
... Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI10 X...AI17 X X X X X No Fix Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line AI18 X X X X X No Fix ...-canonical Address May have Non-deterministic Results AI23 X X X X Fixed VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field AI24...Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 11 Specification Update
Specification Update
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Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI31 X X X X Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper ...
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI31 X X X X Fixed Performance Monitoring Events for Retired Loads (CBH) and Instructions Retired (C0H) May Not Be Accurate AI32 X X X X X No Fix Upper ...
Specification Update
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Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI52 X X X X X No Fix Last Branch Records (LBR) Updates May ...AI56 X X X X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior AI57 X X X X Fixed BTS Message May Be Lost When the STPCLK# Signal is Active AI58 X X X X X... Event FP_ASSIST May Not be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI52 X X X X X No Fix Last Branch Records (LBR) Updates May ...AI56 X X X X Fixed Update of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior AI57 X X X X Fixed BTS Message May Be Lost When the STPCLK# Signal is Active AI58 X X X X X... Event FP_ASSIST May Not be Set for Non-Single-Step #DB Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 13 Specification Update
Specification Update
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...X Fixed REP Store Instructions in a Specific Situation may cause the Processor to Hang AI80 X X X X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate AI81 X X X X X No... Non-root Operation Could Result in Unexpected Behavior AI89 X X X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions AI90 X X X X X No Fix Page Access Bit May be Set ... and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
...X Fixed REP Store Instructions in a Specific Situation may cause the Processor to Hang AI80 X X X X X No Fix Performance Monitoring Events for L1 and L2 Miss May Not be Accurate AI81 X X X X X No... Non-root Operation Could Result in Unexpected Behavior AI89 X X X X X No Fix INVLPG Operation for Large (2M/4M) Pages May be Incomplete under Certain Conditions AI90 X X X X X No Fix Page Access Bit May be Set ... and SYSRET 14 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
Specification Update
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Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI96 X X X X X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction AI97 X X X X X No Fix ... Result in a Processor Hang AI115 X X X X X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache AI116 X X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 ...
Summary Tables of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI96 X X X X X No Fix Performance Monitoring Event SIMD_UOP_TYPE_EXEC.MUL is Counted Incorrectly for PMULUDQ Instruction AI97 X X X X X No Fix ... Result in a Processor Hang AI115 X X X X X No Fix Instruction Fetch May Cause a Livelock During Snoops of the L1 Data Cache AI116 X X X X X No Fix Use of Memory Aliasing with Inconsistent Memory Type may Cause a System Hang or a Machine Check Exception Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 ...
Specification Update
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...Invalidation Number DOCUMENTATION CHANGES - There are no Specification Changes in this Specification Update revision. Number SPECIFICATION CLARIFICATIONS AI1 Clarification of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI117 X X X X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to ... X Fixed (30AH) and MSR_PERF_FIXED_CTR2 (30BH) are no Documentation Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
...Invalidation Number DOCUMENTATION CHANGES - There are no Specification Changes in this Specification Update revision. Number SPECIFICATION CLARIFICATIONS AI1 Clarification of Changes NO B1 B2 L2 M0 G0 Plan ERRATA AI117 X X X X X No Fix A WB Store Following a REP STOS/MOVS or FXSAVE May Lead to ... X Fixed (30AH) and MSR_PERF_FIXED_CTR2 (30BH) are no Documentation Changes in this Specification Update revision. § 16 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update
Specification Update
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Intel® Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB INTEL M ©'05 E4500 INTEL® CORE™2 DUO SLxxx [COO] 2.20GHZ/2M/800/06 [FPO] e4 ATPO S/N Figure 2. Identification Information Identification Information Figure 1. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.13GHZ/2M/1066/06 [FPO] e4 ATPO S/N Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 17 Specification Update
Intel® Core™2 Duo Desktop Processor 2M SKU Package with 800 MHz FSB INTEL M ©'05 E4500 INTEL® CORE™2 DUO SLxxx [COO] 2.20GHZ/2M/800/06 [FPO] e4 ATPO S/N Figure 2. Identification Information Identification Information Figure 1. Intel® Core™2 Duo Desktop Processor 2M SKU Package with 1066 MHz FSB INTEL M ©'05 INTEL® CORE™2 DUO 6400 SLxxx [COO] 2.13GHZ/2M/1066/06 [FPO] e4 ATPO S/N Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 17 Specification Update
Specification Update
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Cache and TLB descriptor parameters are applicable to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register. These processors support the 775_VR_CONFIG_05B specifications 3. NOTES: 1. These parts have PROCHOT# enabled 8. Component Identification Information Component Identification Information The Intel® Core™2 Extreme processor... field of 8W 20 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence ...
Cache and TLB descriptor parameters are applicable to bits [7:4] of the EDX register after RESET, bits [7:4] of the EAX register after the CPUID instruction is executed with a 1 in the EAX register. These processors support the 775_VR_CONFIG_05B specifications 3. NOTES: 1. These parts have PROCHOT# enabled 8. Component Identification Information Component Identification Information The Intel® Core™2 Extreme processor... field of 8W 20 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence ...
Specification Update
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... 2. Intel® Core™2 Duo Desktop Processor 4M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SLA4U B2 4M 06F6h E6320 SLA4T B2 4M 06F6h E6420 SL9S8 B2 4M 06F6h E6600 SL9ZL B2 4M 06F6h E6600 SL9S7 B2 4M 06F6h E6700 SL9ZF B2 4M 06F6h E6700 Speed Core/Bus 1.86 GHz / 1066 MHz 2.13 GHz / 1066 MHz 2.4 GHz / 1066 MHz 2.4 GHz / 1066 MHz 2.66 GHz...
... 2. Intel® Core™2 Duo Desktop Processor 4M SKU Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SLA4U B2 4M 06F6h E6320 SLA4T B2 4M 06F6h E6420 SL9S8 B2 4M 06F6h E6600 SL9ZL B2 4M 06F6h E6600 SL9S7 B2 4M 06F6h E6700 SL9ZF B2 4M 06F6h E6700 Speed Core/Bus 1.86 GHz / 1066 MHz 2.13 GHz / 1066 MHz 2.4 GHz / 1066 MHz 2.4 GHz / 1066 MHz 2.66 GHz...
Specification Update
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... Information Table 2. Intel® Core™2 Extreme Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9S5 B2 4M 06F6h X6800 Speed Core/Bus 2.93 GHz / 1066 MHz Package 775-land LGA Notes 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 22 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Intel® Core™2 Duo Desktop Processor 4M SKU Identification...
... Information Table 2. Intel® Core™2 Extreme Processor Identification Information S-Spec Core Stepping L2 Cache Size (bytes) Processor Signature Processor Number SL9S5 B2 4M 06F6h X6800 Speed Core/Bus 2.93 GHz / 1066 MHz Package 775-land LGA Notes 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 15 22 Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Specification Update Intel® Core™2 Duo Desktop Processor 4M SKU Identification...
Specification Update
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.... Implication: Software should not be taken on the value reported in MCi_ADDR, for Single-bit L2 ECC errors. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 23 Specification Update Workaround: None identified. Under some scenarios, the address reported...with it, even if that vector the system will be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in -service register and mask all interrupts at the same or lower priority. AI2. This ...
.... Implication: Software should not be taken on the value reported in MCi_ADDR, for Single-bit L2 ECC errors. Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence 23 Specification Update Workaround: None identified. Under some scenarios, the address reported...with it, even if that vector the system will be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the address is logged in -service register and mask all interrupts at the same or lower priority. AI2. This ...
