Specification Update
Page 14
...REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP...Old/Out-of-date LBR Information Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Dual-Processor Incompatibility Between B-step and G-step VTPR Write Access... a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP...Old/Out-of-date LBR Information Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Dual-Processor Incompatibility Between B-step and G-step VTPR Write Access... a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 17
... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
Specification Update
Page 24
...Processors supporting Intel® Virtualization Technology (Intel® VT) can execute VMCALL from package-resolved C-state • BUS_TRANS_ANY (Event: 70H) - Implication: The processor PECI controller resets to an incorrect state but this erratum, the processor...Summary Tables of Changes. 24 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: VMCALL executed to activate dual-monitor treatment of SMIs ...set to the idle state. The PECI Controller Resets to the local core. AJ25. Due to this erratum, if reserved bits are set to...
...Processors supporting Intel® Virtualization Technology (Intel® VT) can execute VMCALL from package-resolved C-state • BUS_TRANS_ANY (Event: 70H) - Implication: The processor PECI controller resets to an incorrect state but this erratum, the processor...Summary Tables of Changes. 24 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: VMCALL executed to activate dual-monitor treatment of SMIs ...set to the idle state. The PECI Controller Resets to the local core. AJ25. Due to this erratum, if reserved bits are set to...
Specification Update
Page 45
... PEBS records cannot specify the DS (debug store) save area that is for Intel Xeon processor 5300 series, Intel Xeon processor 5100 series must change this condition will be modified as the BSP (Boot Strap Processor) • Will not signal #GP when attempting to set bits 37-36 ... Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Problem: Logging of overlap is running on VMCS revision ID will support thresholdbased error status (IA32_MCG_CAP [bit 11] = 1) Intel® Xeon® Processor 5300 Series 45 ...
... PEBS records cannot specify the DS (debug store) save area that is for Intel Xeon processor 5300 series, Intel Xeon processor 5100 series must change this condition will be modified as the BSP (Boot Strap Processor) • Will not signal #GP when attempting to set bits 37-36 ... Overlap of an Intel® VT APIC Access Page in a Guest with the DS Save Area May Lead to Unpredictable Behavior Problem: Logging of overlap is running on VMCS revision ID will support thresholdbased error status (IA32_MCG_CAP [bit 11] = 1) Intel® Xeon® Processor 5300 Series 45 ...
Data Sheet
Page 2
... Copyright © 2006, Intel Corporation 2 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Intel may not be found at http://www.intel.com. Current characterized errata are trademarks or registered trademarks of Intel Corporation or its subsidiaries in...configurations. Check with a processor, chipset, BIOS, OS, device drivers and applications enabled for more information. Processor will vary depending on request. Intel, Pentium, Intel Xeon, Enhanced Intel SpeedStep Technology, Intel Virtualization Technology (Intel VT) and Intel logo are available on your...
... Copyright © 2006, Intel Corporation 2 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Intel may not be found at http://www.intel.com. Current characterized errata are trademarks or registered trademarks of Intel Corporation or its subsidiaries in...configurations. Check with a processor, chipset, BIOS, OS, device drivers and applications enabled for more information. Processor will vary depending on request. Intel, Pentium, Intel Xeon, Enhanced Intel SpeedStep Technology, Intel Virtualization Technology (Intel VT) and Intel logo are available on your...
Data Sheet
Page 12
... and supplies the correct voltage and current to the processor and is , unsealed packaging or a device removed from the processor's Digital Thermal Sensor (DTS). The values are a superset of the processor VID bits. 12 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Processors may be connected to the processor based on the logic state of the package. It...
... and supplies the correct voltage and current to the processor and is , unsealed packaging or a device removed from the processor's Digital Thermal Sensor (DTS). The values are a superset of the processor VID bits. 12 Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Processors may be connected to the processor based on the logic state of the package. It...