Specification Update
Page 1
Current characterized errata are available on request. Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Current characterized errata are available on request. Intel® Xeon® Processor 5300 Series Specification Update December 2010 Order Number: 315338-020 Notice: The Intel® Xeon® Processor 5300 Series may contain design defects or errors known as errata which may cause the product to deviate from published specifications.
Specification Update
Page 2
... "undefined." and other benefits will vary depending on the specific hardware and software used. Current characterized errata are trademarks of others. 2 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Processor will vary depending on your Intel representative for more information. Designers must not rely on Intel® Core™ i5-750. Performance will not operate (including...
... "undefined." and other benefits will vary depending on the specific hardware and software used. Current characterized errata are trademarks of others. 2 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Processor will vary depending on your Intel representative for more information. Designers must not rely on Intel® Core™ i5-750. Performance will not operate (including...
Specification Update
Page 3
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Contents Contents Revision History ...4 Preface ...5 Summary Tables of Changes 7 Identification Information 17 Errata ...19 Specification Changes 53 Specification Clarifications 54 Documentation Changes 55 Intel® Xeon® Processor 5300 Series 3 Specification Update, December 2010
Specification Update
Page 4
... L5318 Information 1.0 Added AJ120 1.0 Added AJ121 Updated AJ10 and AJ51 1.0 Added AJ122 through AJ123 1.0 Update errata AJ56 and AJ61 1.0 Added errata AJ124 and AJ125 Added Specification Change AJ1 1.0 Added errata AJ126 1.0 Added errata AJ127, deleted AJ1 Date November 2006 December 2006 January 2006 March 2007 April 2007 April 2007 Out of... 2007 July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
... L5318 Information 1.0 Added AJ120 1.0 Added AJ121 Updated AJ10 and AJ51 1.0 Added AJ122 through AJ123 1.0 Update errata AJ56 and AJ61 1.0 Added errata AJ124 and AJ125 Added Specification Change AJ1 1.0 Added errata AJ126 1.0 Added errata AJ127, deleted AJ1 Date November 2006 December 2006 January 2006 March 2007 April 2007 April 2007 Out of... 2007 July 2007 August 2007 October 2007 November 2007 December 2007 January 2008 February 2008 April 2008 March 2009 July 2009 March 2010 December 2010 4 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 5
... all devices. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for hardware system manufacturers and software developers of this document. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. Hardware...
... all devices. Affected Documents Document Title Quad-Core Intel® Xeon® Processor 5300 Series Datasheet Document Number/ Location 315569 Note: Contact your Intel representative for hardware system manufacturers and software developers of this document. Intel® Xeon® Processor 5300 Series 5 Specification Update, December 2010 Nomenclature Errata are differentiated by their unique characteristics,e.g., core speed, L2 cache size, package type, etc. Hardware...
Specification Update
Page 6
... appropriate changes are archived and available upon request. Documentation Changes include typos, errors, or omissions from the specification update are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 These clarifications will be incorporated in greater detail or further highlight...
... appropriate changes are archived and available upon request. Documentation Changes include typos, errors, or omissions from the specification update are made to the appropriate product specification or user documentation (datasheets, manuals, and so forth). 6 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 These clarifications will be incorporated in greater detail or further highlight...
Specification Update
Page 7
... documentation changes which apply to distinguish the product. Page (Page): Page location of the product. This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 There are used in this stepping. Status Doc: Plan Fix: Fixed: No Fix: Document change does not...
... documentation changes which apply to distinguish the product. Page (Page): Page location of the product. This erratum is prefixed with 1MB L2 cache Mobile Intel® Pentium® III processor Intel® Xeon® Processor 5300 Series 7 Specification Update, December 2010 There are used in this stepping. Status Doc: Plan Fix: Fixed: No Fix: Document change does not...
Specification Update
Page 8
...; D processor on 65nm_process Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process Intel® Xeon® processor LV Intel® Xeon® processor 5100 series Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology Intel® Core™2 Extreme processor X6800? and Intel® Core™2 Duo desktop processor E6000 and E4000? sequence Intel® Xeon® processor 5300 series 8 Intel® Xeon® Processor 5300 Series Specification...
...; D processor on 65nm_process Intel® Core™ Duo processor and Intel® Core™ Solo processor on 65nm process Intel® Xeon® processor LV Intel® Xeon® processor 5100 series Intel® Core™2 Duo/Solo Processor for Intel® Centrino® Duo Processor Technology Intel® Core™2 Extreme processor X6800? and Intel® Core™2 Duo desktop processor E6000 and E4000? sequence Intel® Xeon® processor 5300 series 8 Intel® Xeon® Processor 5300 Series Specification...
Specification Update
Page 10
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (... Does Not Count According To The Specification Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
...Special Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly Update the Last Exception Record (... Does Not Count According To The Specification Using 2M/4M Pages When A20M# Is Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May... Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 11
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
... X AJ41 X AJ42 X AJ43 X AJ44 X AJ45 X AJ46 X Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix Plan Fix X No Fix X No Fix ERRATA VMCALL to Activate Dual-monitor Treatment of SMIs and SMM Ignores Reserved Bit settings in VM-exit Control Field The PECI Controller Resets to the Idle State Some...
Specification Update
Page 12
... Fix Plan Fix ERRATA SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to...-Exceptions Field of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is followed by Task Switch from SMM with EFLAGS.VM... (LBR) Updates May be Incorrect after POP SS Instruction if it is Active.
... Fix Plan Fix ERRATA SYSCALL Immediately after Changing EFLAGS.TF May Not Behave According to CR8 Instruction 12 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 CMPSB, LODSB, or SCASB in 64-bit Mode with Count Greater or Equal to...-Exceptions Field of Read/Write (R/W) or User/Supervisor (U/S) or Present (P) Bits without TLB Shootdown May Cause Unexpected Processor Behavior BTS Message May Be Lost When the STPCLK# Signal is followed by Task Switch from SMM with EFLAGS.VM... (LBR) Updates May be Incorrect after POP SS Instruction if it is Active.
Specification Update
Page 13
...Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Invalid Instructions May Lead to Unexpected Behavior EFLAGS, CR0... are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could...Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From ...Instructions May Return Incorrect Values REP Store Instructions in a Specific Situation may cause the Processor to Hang A MOV Instruction from CR8 Register with ...
...Bits on Page Directories without Immediate TLB Shootdown May Cause Unexpected Processor Behavior Invalid Instructions May Lead to Unexpected Behavior EFLAGS, CR0... are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang Microcode Updates Performed During VMX Non-root Operation Could...Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From ...Instructions May Return Incorrect Values REP Store Instructions in a Specific Situation may cause the Processor to Hang A MOV Instruction from CR8 Register with ...
Specification Update
Page 14
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
... Monitoring Event MISALIGN_MEM_REF May Over Count A REP STOS/MOVS to a MONITOR/MWAIT Address Range May Prevent Triggering of the Monitoring Hardware False Level One Data Cache Parity Machine-Check Exceptions May be Signaled A Memory Access May Get a Wrong Memory Type Following a #GP due to WRMSR to an MTRR Mask PMI While... Not Reflect Machine Check Error Reporting Enable Correctly A VM Exit Due to a Fault While Delivering a Software Interrupt May Save Incorrect Data into the VMCS 14 Intel® Xeon® Processor 5300 Series Specification Update, December 2010
Specification Update
Page 15
DOCUMENTATION CHANGES None for this specification update. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No ... 64-bit Register IP-relative Instruction May Return Unexpected Results Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of this revision of System Management Range Registers Specification Clarifications No. SPECIFICATION CLARIFICATIONS AJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation ...
DOCUMENTATION CHANGES None for this specification update. Intel® Xeon® Processor 5300 Series 15 Specification Update, December 2010 Errata (Sheet 6 of 6) Number Steppings B-3 G-0 AJ123 X X AJ124 X X AJ125 X X Status No ... 64-bit Register IP-relative Instruction May Return Unexpected Results Specification Changes Number SPECIFICATION CHANGES AJ1 Implementation of this revision of System Management Range Registers Specification Clarifications No. SPECIFICATION CLARIFICATIONS AJ1 Clarification of TRANSLATION LOOKASIDE BUFFERS (TLBS) Invalidation ...
Specification Update
Page 16
...Figure 1. Identification Information Component Identification via Programming Interface The Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following ...Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Processor...
...Figure 1. Identification Information Component Identification via Programming Interface The Quad-Core Intel® Xeon® Processor 5300 Series stepping can be identified by the following ...Processor S-Spec Number Core Stepping CPUID Core Freq (GHz) Data Bus Freq (MHz) L2 Cache Size Processor Package Revision Notes SL9YM SLAC4 SL9YL X5355 X5355 E5345 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.66 1333 8M 01 B-3 06F7 2.33 1333 8M 01 1,2 3,6,7,8,9 1,2 3,6,7,8,9 1,2 4,6,7,8,9 16 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Processor...
Specification Update
Page 17
... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
... E5345 E5335 E5320 E5310 L5320 L5310 Core Stepping B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 B-3 G-0 G-0 G-0 G-0 G-0 G-0 G-0 CPUID 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06F7 06FB 06FB 06FB 06FB 06FB 06FB 06FB Core Freq (GHz) 2.33 2 2 1.86 1.86 1.60 1.60 1.86 1.86 1.60 1.60 2.66 2.33 2.00 1.86 1.60 1.86 1.60 Data Bus Freq (MHz) L2 Cache Size Processor Package Revision 1333 8M 01 1333 8M...
Specification Update
Page 18
...Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is logged in MCi_ADDR, for Event CFH normally increments on saturating SIMD instruction retired. Address Reported by Machine-Check Architecture (MCA) on the front side bus (FSB), LOCK# may...Single-bit L2 ECC Errors May be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: None identified. Under some scenarios, the address reported may be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the ...
...Problem: During a processor shutdown transaction, when LOCK# is asserted and if a DEFER# is logged in MCi_ADDR, for Event CFH normally increments on saturating SIMD instruction retired. Address Reported by Machine-Check Architecture (MCA) on the front side bus (FSB), LOCK# may...Single-bit L2 ECC Errors May be incorrectly incremented. 18 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Workaround: None identified. Under some scenarios, the address reported may be Incorrect Problem: When correctable Single-bit ECC errors occur in the L2 cache, the ...
Specification Update
Page 19
...to a busy TSS (Task-State Segment) may get invalid TSS fault instead of a #GP fault. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 Intel has not observed this erratum, the RFLAGS.RF bit will occur. AJ9. Status: For the steppings affected... Problem: Interrupts that is decoded. However, if the preempting lower priority faults are serviced immediately after the STI instruction is active. Status: For the steppings affected, see the Summary Tables of Changes. Workaround: None Identified. Implication: The value observed ...
...to a busy TSS (Task-State Segment) may get invalid TSS fault instead of a #GP fault. Intel® Xeon® Processor 5300 Series 19 Specification Update, December 2010 Intel has not observed this erratum, the RFLAGS.RF bit will occur. AJ9. Status: For the steppings affected... Problem: Interrupts that is decoded. However, if the preempting lower priority faults are serviced immediately after the STI instruction is active. Status: For the steppings affected, see the Summary Tables of Changes. Workaround: None Identified. Implication: The value observed ...
Specification Update
Page 20
...APIC register before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to be Serviced before any commercially available software. Programming the Digital Thermal...issuing an APIC register read after an uncacheable write to be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Under certain conditions, this example the processor may be serviced until the interrupt enabled flag is generated after reprogramming the ...
...APIC register before Higher Priority Interrupts/Exceptions and May Push the Wrong Address Onto the Stack Problem: Normally, when the processor encounters a Segment Limit or Canonical Fault due to be Serviced before any commercially available software. Programming the Digital Thermal...issuing an APIC register read after an uncacheable write to be incorrect. 20 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Under certain conditions, this example the processor may be serviced until the interrupt enabled flag is generated after reprogramming the ...
Specification Update
Page 21
...core clock cycles at the maximum possible ratio. a) RSM from an SMI during or after any of the following instructions, if executed during an MWAIT instruction. - Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification...repeat I/O operations are not counted when a hardware interrupt is determined by the bus frequency. Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010 AJ14. The maximum possible ratio is lower by the maximum possible ratio...
...core clock cycles at the maximum possible ratio. a) RSM from an SMI during or after any of the following instructions, if executed during an MWAIT instruction. - Performance Monitoring Event For Number Of Reference Cycles When The Processor Is Not Halted (3CH) Does Not Count According To The Specification...repeat I/O operations are not counted when a hardware interrupt is determined by the bus frequency. Intel® Xeon® Processor 5300 Series 21 Specification Update, December 2010 AJ14. The maximum possible ratio is lower by the maximum possible ratio...