Specification Update
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...,e.g., core speed, L2 cache size, package type, etc. Hardware and software designed to deviate from published specifications. This document is intended for that was not previously published. This document may cause the Intel® Xeon® Processor 5300...Intel® Processor Identification and the CPUID Instruction 241618 Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M Intel® 64 and IA-32 Architectures...
...,e.g., core speed, L2 cache size, package type, etc. Hardware and software designed to deviate from published specifications. This document is intended for that was not previously published. This document may cause the Intel® Xeon® Processor 5300...Intel® Processor Identification and the CPUID Instruction 241618 Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 1: Basic Architecture Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 2A: Instruction Set Reference Manual A-M Intel® 64 and IA-32 Architectures...
Specification Update
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... Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly ...Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment... Restoring the Architectural State from SMRAM Sequential Code Fetch to Non-canonical Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, ...
... Cycle Shutdown Transaction May Unexpectedly De-assert Address Reported by Machine-Check Architecture (MCA) on Singlebit L2 ECC Errors May be Incorrect VERW/VERR/LSL/LAR Instructions May Unexpectedly ...Asserted May Result in Incorrect Address Translations Writing Shared Unaligned Data that Crosses a Cache Line without Proper Semaphores or Barriers May Expose a Memory Ordering Issue Code Segment... Restoring the Architectural State from SMRAM Sequential Code Fetch to Non-canonical Address May have Nondeterministic Results 10 Intel® Xeon® Processor 5300 Series Specification Update, ...
Specification Update
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...CPUID Reports Architectural Performance Monitoring Version 2 is Supported, When Only Version 1 Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang...Hang A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63:16 of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010 Errata (Sheet 4 of 6) Number Steppings B-3 G-0 AJ73 X X AJ74 ...Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction ...
...CPUID Reports Architectural Performance Monitoring Version 2 is Supported, When Only Version 1 Capabilities are Available Unaligned Accesses to Paging Structures May Cause the Processor to Hang...Hang A MOV Instruction from CR8 Register with 16 Bit Operand Size Will Leave Bits 63:16 of MOV SS or STI Intel® Xeon® Processor 5300 Series 13 Specification Update, December 2010 Errata (Sheet 4 of 6) Number Steppings B-3 G-0 AJ73 X X AJ74 ...Properly Cleared After Code Breakpoint Performance Monitoring Events for L1 and L2 Miss May Not be Accurate BTM/BTS Branch-From Instruction ...
Specification Update
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...LAR instructions. Workaround: Software exception handlers that rely on the front side bus (FSB), LOCK# may be inaccurate if VERW/VERR/LSL/LAR instructions are executed after... in MCi_ADDR, for Event CFH normally increments on the value reported in the L2 cache, the address is pipelined on the LER MSR value should not rely on ...L2 ECC errors. Status: Deleted AJ2. Address Reported by Machine-Check Architecture (MCA) on Single-bit L2 ECC Errors May be incorrect. Under some scenarios, the address reported may be incorrectly incremented. 18 Intel® Xeon® Processor...
...LAR instructions. Workaround: Software exception handlers that rely on the front side bus (FSB), LOCK# may be inaccurate if VERW/VERR/LSL/LAR instructions are executed after... in MCi_ADDR, for Event CFH normally increments on the value reported in the L2 cache, the address is pipelined on the LER MSR value should not rely on ...L2 ECC errors. Status: Deleted AJ2. Address Reported by Machine-Check Architecture (MCA) on Single-bit L2 ECC Errors May be incorrect. Under some scenarios, the address reported may be incorrectly incremented. 18 Intel® Xeon® Processor...
Specification Update
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...of Changes. canonical address 0000800000000000), under some circumstances the code fetch will be avoided by RSM instruction before Restoring the Architectural State from SMRAM Problem: The Resume from System Management Mode (RSM) instruction does not flush global pages from address ...on the internal pipelining and execution state of the instructions found there. Problem: Implication: Sequential Code Fetch to non- Intel® Xeon® Processor 5300 Series 23 Specification Update, December 2010 The PE bit of the FPU status word may transfer control to a canonical...
...of Changes. canonical address 0000800000000000), under some circumstances the code fetch will be avoided by RSM instruction before Restoring the Architectural State from SMRAM Problem: The Resume from System Management Mode (RSM) instruction does not flush global pages from address ...on the internal pipelining and execution state of the instructions found there. Problem: Implication: Sequential Code Fetch to non- Intel® Xeon® Processor 5300 Series 23 Specification Update, December 2010 The PE bit of the FPU status word may transfer control to a canonical...
Specification Update
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... memory state may be terminated by a locked store which is split across cache lines within the address range used to Partial Memory Update Problem: A partial...Implication: After an MCE event, accesses to the memory limit violation as detailed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, Section: Handling Self- Workaround: Software ... these MSRs may contain incorrect data. Intel® Xeon® Processor 5300 Series 27 Specification Update, December 2010 Implication: The logical processor that wrap around the respective 16-bit...
... memory state may be terminated by a locked store which is split across cache lines within the address range used to Partial Memory Update Problem: A partial...Implication: After an MCE event, accesses to the memory limit violation as detailed in the Intel Architecture Software Developer's Manual Volume 3: System Programming Guide, Section: Handling Self- Workaround: Software ... these MSRs may contain incorrect data. Intel® Xeon® Processor 5300 Series 27 Specification Update, December 2010 Implication: The logical processor that wrap around the respective 16-bit...
Specification Update
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... that reads from an I /O instruction if the platform has not been configured to the default value. AJ52. AJ53. Intel® Xeon® Processor 5300 Series 31 Specification Update, December 2010 AJ50. Last Branch Records (LBR) Updates May be executed atomically. IO_SMI Indication ... Problem: A Task-State Segment (TSS) task switch may be aware of Changes. Workaround: As recommended in the IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS/POP SS in incorrect signaling of the following instruction should initialize IA32_FMASK after...
... that reads from an I /O instruction if the platform has not been configured to the default value. AJ52. AJ53. Intel® Xeon® Processor 5300 Series 31 Specification Update, December 2010 AJ50. Last Branch Records (LBR) Updates May be executed atomically. IO_SMI Indication ... Problem: A Task-State Segment (TSS) task switch may be aware of Changes. Workaround: As recommended in the IA32 Intel® Architecture Software Developer's Manual, the use of MOV SS/POP SS in incorrect signaling of the following instruction should initialize IA32_FMASK after...
Specification Update
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...Active Problem: STPCLK# is present in TLB when INIT occurs Implication: Software may encounter unexpected page fault or incorrect address translation due to a TLB entry erroneously left in conjunction with a complex sequence of internal processor micro-architectural.... Implication: BTS messages may lead to Multiple Processors" in volume 3A of the IA-32 Intel® Architecture Software Developer's Manual), in TLB after INIT.... Implication: Software that uses aliasing of Changes. 32 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 AJ57. Memory...
...Active Problem: STPCLK# is present in TLB when INIT occurs Implication: Software may encounter unexpected page fault or incorrect address translation due to a TLB entry erroneously left in conjunction with a complex sequence of internal processor micro-architectural.... Implication: BTS messages may lead to Multiple Processors" in volume 3A of the IA-32 Intel® Architecture Software Developer's Manual), in TLB after INIT.... Implication: Software that uses aliasing of Changes. 32 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 AJ57. Memory...
Specification Update
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...Combining Memory Locations" will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in comparison to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section "Buffering of Changes. Implication: Software that conforms to which...on paging structure entries, accessing a portion of two different entries simultaneously, the processor may observe data in the Architectural Performance Monitoring section of Changes. AJ82. Intel® Xeon® Processor 5300 Series 39 Specification Update, December 2010 Status: For the steppings affected, see...
...Combining Memory Locations" will observe an incorrect version number in CPUID.0Ah.EAX [7:0] in comparison to the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A, section "Buffering of Changes. Implication: Software that conforms to which...on paging structure entries, accessing a portion of two different entries simultaneously, the processor may observe data in the Architectural Performance Monitoring section of Changes. AJ82. Intel® Xeon® Processor 5300 Series 39 Specification Update, December 2010 Status: For the steppings affected, see...
Specification Update
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...processor may lead to invalid instructions. Workaround: Software should ensure that the memory type specified in the MTRRs is present in "Propagation of Page Table and Page Directory Entry Changes to unexpected behavior. Status: For the steppings affected, see the Summary Tables of the Intel® 64 and IA-32 Architecture...a code page, then due to this erratum with a complex sequence of Changes. 40 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Intel has not observed this erratum the memory page Access bit (A bit) may lead to general...
...processor may lead to invalid instructions. Workaround: Software should ensure that the memory type specified in the MTRRs is present in "Propagation of Page Table and Page Directory Entry Changes to unexpected behavior. Status: For the steppings affected, see the Summary Tables of the Intel® 64 and IA-32 Architecture...a code page, then due to this erratum with a complex sequence of Changes. 40 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Intel has not observed this erratum the memory page Access bit (A bit) may lead to general...
Specification Update
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...Architectures Optimization Reference Manual. AJ96. This may be asserted. Problem: Storage of PEBS Record Delayed Following Execution of MOV SS or STI When a performance monitoring counter is configured for PMULUDQ micro-ops may be Incorrect after Shutdown Problem: When the processor is active...count value returned by the performance monitoring counter MACRO_INST.DECODED may still be Incorrect as described in the PEBS Intel® Xeon® Processor 5300 Series 41 Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of ...
...Architectures Optimization Reference Manual. AJ96. This may be asserted. Problem: Storage of PEBS Record Delayed Following Execution of MOV SS or STI When a performance monitoring counter is configured for PMULUDQ micro-ops may be Incorrect after Shutdown Problem: When the processor is active...count value returned by the performance monitoring counter MACRO_INST.DECODED may still be Incorrect as described in the PEBS Intel® Xeon® Processor 5300 Series 41 Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of ...
Specification Update
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... to this erratum, code #PF may not drain the WC buffers. Code Segment Limit Violation #GP and code #PF 42 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of MOV SS or STI. Workaround...Die Termination always disabled meaning the VOL of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the PEBS record represents the state of the next instruction to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods ...
... to this erratum, code #PF may not drain the WC buffers. Code Segment Limit Violation #GP and code #PF 42 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Status: For the steppings affected, see the Summary Tables of MOV SS or STI. Workaround...Die Termination always disabled meaning the VOL of Caching Available", WP (Write Protected) stores should drain the WC (Write Combining) buffers in the PEBS record represents the state of the next instruction to Intel® 64 and IA-32 Intel Architecture Software Developer's Manual, Volume 3A "Methods ...
Specification Update
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...by having more than the TPR-threshold VM-execution control field. Intel® Xeon® Processor 5300 Series 47 Specification Update, December 2010 If the cacheable address... shadow", "activate secondary controls", and "virtualize APIC accesses" VM-execution controls all set to VMM software prematurely injecting an interrupt into the instruction cache, and the...architectural event that implements memory aliasing by STI and bit 1 - AJ113. Use of those bits is fetched in this practice as "fast strings") for synchronization. This may lead to 1 and with different cache...
...by having more than the TPR-threshold VM-execution control field. Intel® Xeon® Processor 5300 Series 47 Specification Update, December 2010 If the cacheable address... shadow", "activate secondary controls", and "virtualize APIC accesses" VM-execution controls all set to VMM software prematurely injecting an interrupt into the instruction cache, and the...architectural event that implements memory aliasing by STI and bit 1 - AJ113. Use of those bits is fetched in this practice as "fast strings") for synchronization. This may lead to 1 and with different cache...
Specification Update
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...the EFLAGS/RFLAGS register, is higher, software should compare it . 48 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: When this erratum with different memory... types. RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: RSM instruction execution, under certain conditions triggered by a VM-Entry Failure The Intel® 64 and IA-32 Architectures...
...the EFLAGS/RFLAGS register, is higher, software should compare it . 48 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Implication: When this erratum with different memory... types. RSM Instruction Execution under Certain Conditions May Cause Processor Hang or Unexpected Instruction Execution Results Problem: RSM instruction execution, under certain conditions triggered by a VM-Entry Failure The Intel® 64 and IA-32 Architectures...
Specification Update
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...last update to the IA32_MC1_STATUS MSR. Due to Exceptions" of the IA32_MC1_CTL MSR enable bit. Workaround: None identified. Intel® Xeon® Processor 5300 Series 49 Specification Update, December 2010 Status: For affected stepping see the Summary Tables of the last update.... Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Problem: According to the Intel® 64 and IA-32 Architectures ...
...last update to the IA32_MC1_STATUS MSR. Due to Exceptions" of the IA32_MC1_CTL MSR enable bit. Workaround: None identified. Intel® Xeon® Processor 5300 Series 49 Specification Update, December 2010 Status: For affected stepping see the Summary Tables of the last update.... Benign Exception after a Double Fault May Not Cause a Triple Fault Shutdown Problem: According to the Intel® 64 and IA-32 Architectures ...
Specification Update
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... in Intel® 64 and IA-32 Architectures to limit cacheable reference of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide. SMRRs are defined in SMRAM. The SMRR interface can be able to reconfigure an Intel processor to gain access to the following documents: • Quad-Core Intel® Xeon® Processor 5300...
... in Intel® 64 and IA-32 Architectures to limit cacheable reference of the Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide. SMRRs are defined in SMRAM. The SMRR interface can be able to reconfigure an Intel processor to gain access to the following documents: • Quad-Core Intel® Xeon® Processor 5300...
Specification Update
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... this issue. Until that time, an application note, TLBs, Paging-Structure Caches, and Their Invalidation (http:// www.intel.com/products/processor/manuals/index.htm), is needed to the following documents: • Quad-Core Intel® Xeon® Processor 5300 Series Datasheet • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide AJ1. This information...
... this issue. Until that time, an application note, TLBs, Paging-Structure Caches, and Their Invalidation (http:// www.intel.com/products/processor/manuals/index.htm), is needed to the following documents: • Quad-Core Intel® Xeon® Processor 5300 Series Datasheet • Intel® 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide AJ1. This information...
Specification Update
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... this Specification Update revision. § 54 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Documentation Changes The Documentation Changes listed in a separate document Intel® 64 and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link below to the following documents: Quad-Core Intel® Xeon® Processor 5300 Series Datasheet All Documentation Changes will...
... this Specification Update revision. § 54 Intel® Xeon® Processor 5300 Series Specification Update, December 2010 Documentation Changes The Documentation Changes listed in a separate document Intel® 64 and IA-32 Architecture Software Developer's Manual Documentation Changes. Follow the link below to the following documents: Quad-Core Intel® Xeon® Processor 5300 Series Datasheet All Documentation Changes will...
Data Sheet
Page 2
...Intel® 64. Intel, Pentium, Intel Xeon, Enhanced Intel SpeedStep Technology, Intel Virtualization Technology (Intel VT) and Intel logo are available on hardware and software configurations. The Quad-Core Intel® Xeon® Processor 5300 Series may contain design defects or errors known as the property of Intel..., TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. Intel products are referenced in development. Intel® 64 architecture requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and applications enabled...
...Intel® 64. Intel, Pentium, Intel Xeon, Enhanced Intel SpeedStep Technology, Intel Virtualization Technology (Intel VT) and Intel logo are available on hardware and software configurations. The Quad-Core Intel® Xeon® Processor 5300 Series may contain design defects or errors known as the property of Intel..., TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. Intel products are referenced in development. Intel® 64 architecture requires a computer system with a processor, chipset, BIOS, virtual machine monitor (VMM) and applications enabled...
Data Sheet
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... to servers and workstations. Introduction 1 Introduction The Quad-Core Intel® Xeon® Processor 5300 Series are implemented including Thermal Monitor 1 (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep® Technology. Some key features include on Intel's 65 nanometer process technology combining high performance with Advanced Transfer Cache Architecture. The Quad-Core Intel® Xeon® Processor 5300 Series features include Advanced Dynamic Execution...
... to servers and workstations. Introduction 1 Introduction The Quad-Core Intel® Xeon® Processor 5300 Series are implemented including Thermal Monitor 1 (TM1), Thermal Monitor 2 (TM2) and Enhanced Intel SpeedStep® Technology. Some key features include on Intel's 65 nanometer process technology combining high performance with Advanced Transfer Cache Architecture. The Quad-Core Intel® Xeon® Processor 5300 Series features include Advanced Dynamic Execution...